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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4declare void @use32(i32)5 6; Widen a select of constants to eliminate an extend.7 8define i16 @sel_sext_constants(i1 %cmp) {9; CHECK-LABEL: @sel_sext_constants(10; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 -1, i16 4211; CHECK-NEXT: ret i16 [[EXT]]12;13 %sel = select i1 %cmp, i8 255, i8 4214 %ext = sext i8 %sel to i1615 ret i16 %ext16}17 18define i16 @sel_zext_constants(i1 %cmp) {19; CHECK-LABEL: @sel_zext_constants(20; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 255, i16 4221; CHECK-NEXT: ret i16 [[EXT]]22;23 %sel = select i1 %cmp, i8 255, i8 4224 %ext = zext i8 %sel to i1625 ret i16 %ext26}27 28define double @sel_fpext_constants(i1 %cmp) {29; CHECK-LABEL: @sel_fpext_constants(30; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double -2.550000e+02, double 4.200000e+0131; CHECK-NEXT: ret double [[EXT]]32;33 %sel = select i1 %cmp, float -255.0, float 42.034 %ext = fpext float %sel to double35 ret double %ext36}37 38; FIXME: We should not grow the size of the select in the next 4 cases.39 40define i64 @sel_sext(i32 %a, i1 %cmp) {41; CHECK-LABEL: @sel_sext(42; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[A:%.*]] to i6443; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 4244; CHECK-NEXT: ret i64 [[EXT]]45;46 %sel = select i1 %cmp, i32 %a, i32 4247 %ext = sext i32 %sel to i6448 ret i64 %ext49}50 51define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) {52; CHECK-LABEL: @sel_sext_vec(53; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[A:%.*]] to <4 x i64>54; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> splat (i64 42)55; CHECK-NEXT: ret <4 x i64> [[EXT]]56;57 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>58 %ext = sext <4 x i32> %sel to <4 x i64>59 ret <4 x i64> %ext60}61 62define i64 @sel_zext(i32 %a, i1 %cmp) {63; CHECK-LABEL: @sel_zext(64; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i6465; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 4266; CHECK-NEXT: ret i64 [[EXT]]67;68 %sel = select i1 %cmp, i32 %a, i32 4269 %ext = zext i32 %sel to i6470 ret i64 %ext71}72 73define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {74; CHECK-LABEL: @sel_zext_vec(75; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> [[A:%.*]] to <4 x i64>76; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> splat (i64 42)77; CHECK-NEXT: ret <4 x i64> [[EXT]]78;79 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>80 %ext = zext <4 x i32> %sel to <4 x i64>81 ret <4 x i64> %ext82}83 84; FIXME: The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.85; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only86; way to justify widening the select.87 88define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {89; CHECK-LABEL: @trunc_sel_larger_sext(90; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[A:%.*]] to i1691; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i6492; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 4293; CHECK-NEXT: ret i64 [[EXT]]94;95 %trunc = trunc i32 %a to i1696 %sel = select i1 %cmp, i16 %trunc, i16 4297 %ext = sext i16 %sel to i6498 ret i64 %ext99}100 101define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {102; CHECK-LABEL: @trunc_sel_larger_sext_vec(103; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i32> [[A:%.*]] to <2 x i16>104; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i64>105; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>106; CHECK-NEXT: ret <2 x i64> [[EXT]]107;108 %trunc = trunc <2 x i32> %a to <2 x i16>109 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>110 %ext = sext <2 x i16> %sel to <2 x i64>111 ret <2 x i64> %ext112}113 114define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {115; CHECK-LABEL: @trunc_sel_smaller_sext(116; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[A:%.*]] to i16117; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32118; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42119; CHECK-NEXT: ret i32 [[EXT]]120;121 %trunc = trunc i64 %a to i16122 %sel = select i1 %cmp, i16 %trunc, i16 42123 %ext = sext i16 %sel to i32124 ret i32 %ext125}126 127define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {128; CHECK-LABEL: @trunc_sel_smaller_sext_vec(129; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i16>130; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i32>131; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>132; CHECK-NEXT: ret <2 x i32> [[EXT]]133;134 %trunc = trunc <2 x i64> %a to <2 x i16>135 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>136 %ext = sext <2 x i16> %sel to <2 x i32>137 ret <2 x i32> %ext138}139 140define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {141; CHECK-LABEL: @trunc_sel_equal_sext(142; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 16143; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 16144; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42145; CHECK-NEXT: ret i32 [[EXT]]146;147 %trunc = trunc i32 %a to i16148 %sel = select i1 %cmp, i16 %trunc, i16 42149 %ext = sext i16 %sel to i32150 ret i32 %ext151}152 153define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {154; CHECK-LABEL: @trunc_sel_equal_sext_vec(155; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[A:%.*]], splat (i32 16)156; CHECK-NEXT: [[TMP2:%.*]] = ashr exact <2 x i32> [[TMP1]], splat (i32 16)157; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>158; CHECK-NEXT: ret <2 x i32> [[EXT]]159;160 %trunc = trunc <2 x i32> %a to <2 x i16>161 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>162 %ext = sext <2 x i16> %sel to <2 x i32>163 ret <2 x i32> %ext164}165 166define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {167; CHECK-LABEL: @trunc_sel_larger_zext(168; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 [[A:%.*]], 65535169; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TRUNC_MASK]] to i64170; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42171; CHECK-NEXT: ret i64 [[EXT]]172;173 %trunc = trunc i32 %a to i16174 %sel = select i1 %cmp, i16 %trunc, i16 42175 %ext = zext i16 %sel to i64176 ret i64 %ext177}178 179define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {180; CHECK-LABEL: @trunc_sel_larger_zext_vec(181; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and <2 x i32> [[A:%.*]], splat (i32 65535)182; CHECK-NEXT: [[TMP1:%.*]] = zext nneg <2 x i32> [[TRUNC_MASK]] to <2 x i64>183; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>184; CHECK-NEXT: ret <2 x i64> [[EXT]]185;186 %trunc = trunc <2 x i32> %a to <2 x i16>187 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>188 %ext = zext <2 x i16> %sel to <2 x i64>189 ret <2 x i64> %ext190}191 192define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {193; CHECK-LABEL: @trunc_sel_smaller_zext(194; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A:%.*]] to i32195; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535196; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42197; CHECK-NEXT: ret i32 [[EXT]]198;199 %trunc = trunc i64 %a to i16200 %sel = select i1 %cmp, i16 %trunc, i16 42201 %ext = zext i16 %sel to i32202 ret i32 %ext203}204 205define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {206; CHECK-LABEL: @trunc_sel_smaller_zext_vec(207; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>208; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], splat (i32 65535)209; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>210; CHECK-NEXT: ret <2 x i32> [[EXT]]211;212 %trunc = trunc <2 x i64> %a to <2 x i16>213 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>214 %ext = zext <2 x i16> %sel to <2 x i32>215 ret <2 x i32> %ext216}217 218define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {219; CHECK-LABEL: @trunc_sel_equal_zext(220; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 65535221; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42222; CHECK-NEXT: ret i32 [[EXT]]223;224 %trunc = trunc i32 %a to i16225 %sel = select i1 %cmp, i16 %trunc, i16 42226 %ext = zext i16 %sel to i32227 ret i32 %ext228}229 230define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {231; CHECK-LABEL: @trunc_sel_equal_zext_vec(232; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], splat (i32 65535)233; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>234; CHECK-NEXT: ret <2 x i32> [[EXT]]235;236 %trunc = trunc <2 x i32> %a to <2 x i16>237 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>238 %ext = zext <2 x i16> %sel to <2 x i32>239 ret <2 x i32> %ext240}241 242define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {243; CHECK-LABEL: @trunc_sel_larger_fpext(244; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half245; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double246; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double [[TMP1]], double 4.200000e+01247; CHECK-NEXT: ret double [[EXT]]248;249 %trunc = fptrunc float %a to half250 %sel = select i1 %cmp, half %trunc, half 42.0251 %ext = fpext half %sel to double252 ret double %ext253}254 255define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {256; CHECK-LABEL: @trunc_sel_larger_fpext_vec(257; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>258; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>259; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>260; CHECK-NEXT: ret <2 x double> [[EXT]]261;262 %trunc = fptrunc <2 x float> %a to <2 x half>263 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>264 %ext = fpext <2 x half> %sel to <2 x double>265 ret <2 x double> %ext266}267 268define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {269; CHECK-LABEL: @trunc_sel_smaller_fpext(270; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[A:%.*]] to half271; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float272; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01273; CHECK-NEXT: ret float [[EXT]]274;275 %trunc = fptrunc double %a to half276 %sel = select i1 %cmp, half %trunc, half 42.0277 %ext = fpext half %sel to float278 ret float %ext279}280 281define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {282; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(283; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> [[A:%.*]] to <2 x half>284; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>285; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>286; CHECK-NEXT: ret <2 x float> [[EXT]]287;288 %trunc = fptrunc <2 x double> %a to <2 x half>289 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>290 %ext = fpext <2 x half> %sel to <2 x float>291 ret <2 x float> %ext292}293 294define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {295; CHECK-LABEL: @trunc_sel_equal_fpext(296; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half297; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float298; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01299; CHECK-NEXT: ret float [[EXT]]300;301 %trunc = fptrunc float %a to half302 %sel = select i1 %cmp, half %trunc, half 42.0303 %ext = fpext half %sel to float304 ret float %ext305}306 307define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {308; CHECK-LABEL: @trunc_sel_equal_fpext_vec(309; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>310; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>311; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>312; CHECK-NEXT: ret <2 x float> [[EXT]]313;314 %trunc = fptrunc <2 x float> %a to <2 x half>315 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>316 %ext = fpext <2 x half> %sel to <2 x float>317 ret <2 x float> %ext318}319 320define i32 @test_sext1(i1 %cca, i1 %ccb) {321; CHECK-LABEL: @test_sext1(322; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 [[CCA:%.*]], i1 false323; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32324; CHECK-NEXT: ret i32 [[R]]325;326 %ccax = sext i1 %cca to i32327 %r = select i1 %ccb, i32 %ccax, i32 0328 ret i32 %r329}330 331define i32 @test_sext2(i1 %cca, i1 %ccb) {332; CHECK-LABEL: @test_sext2(333; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 true, i1 [[CCA:%.*]]334; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32335; CHECK-NEXT: ret i32 [[R]]336;337 %ccax = sext i1 %cca to i32338 %r = select i1 %ccb, i32 -1, i32 %ccax339 ret i32 %r340}341 342define i32 @test_sext3(i1 %cca, i1 %ccb) {343; CHECK-LABEL: @test_sext3(344; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true345; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 [[CCA:%.*]], i1 false346; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32347; CHECK-NEXT: ret i32 [[R]]348;349 %ccax = sext i1 %cca to i32350 %r = select i1 %ccb, i32 0, i32 %ccax351 ret i32 %r352}353 354define i32 @test_sext4(i1 %cca, i1 %ccb) {355; CHECK-LABEL: @test_sext4(356; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true357; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 true, i1 [[CCA:%.*]]358; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32359; CHECK-NEXT: ret i32 [[R]]360;361 %ccax = sext i1 %cca to i32362 %r = select i1 %ccb, i32 %ccax, i32 -1363 ret i32 %r364}365 366define i32 @test_zext1(i1 %cca, i1 %ccb) {367; CHECK-LABEL: @test_zext1(368; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 [[CCA:%.*]], i1 false369; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32370; CHECK-NEXT: ret i32 [[R]]371;372 %ccax = zext i1 %cca to i32373 %r = select i1 %ccb, i32 %ccax, i32 0374 ret i32 %r375}376 377define i32 @test_zext2(i1 %cca, i1 %ccb) {378; CHECK-LABEL: @test_zext2(379; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 true, i1 [[CCA:%.*]]380; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32381; CHECK-NEXT: ret i32 [[R]]382;383 %ccax = zext i1 %cca to i32384 %r = select i1 %ccb, i32 1, i32 %ccax385 ret i32 %r386}387 388define i32 @test_zext3(i1 %cca, i1 %ccb) {389; CHECK-LABEL: @test_zext3(390; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true391; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 [[CCA:%.*]], i1 false392; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32393; CHECK-NEXT: ret i32 [[R]]394;395 %ccax = zext i1 %cca to i32396 %r = select i1 %ccb, i32 0, i32 %ccax397 ret i32 %r398}399 400define i32 @test_zext4(i1 %cca, i1 %ccb) {401; CHECK-LABEL: @test_zext4(402; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true403; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 true, i1 [[CCA:%.*]]404; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32405; CHECK-NEXT: ret i32 [[R]]406;407 %ccax = zext i1 %cca to i32408 %r = select i1 %ccb, i32 %ccax, i32 1409 ret i32 %r410}411 412define i32 @test_negative_sext(i1 %a, i1 %cc) {413; CHECK-LABEL: @test_negative_sext(414; CHECK-NEXT: [[A_EXT:%.*]] = sext i1 [[A:%.*]] to i32415; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 1416; CHECK-NEXT: ret i32 [[R]]417;418 %a.ext = sext i1 %a to i32419 %r = select i1 %cc, i32 %a.ext, i32 1420 ret i32 %r421}422 423define i32 @test_negative_zext(i1 %a, i1 %cc) {424; CHECK-LABEL: @test_negative_zext(425; CHECK-NEXT: [[A_EXT:%.*]] = zext i1 [[A:%.*]] to i32426; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -1427; CHECK-NEXT: ret i32 [[R]]428;429 %a.ext = zext i1 %a to i32430 %r = select i1 %cc, i32 %a.ext, i32 -1431 ret i32 %r432}433 434define i32 @test_bits_sext(i8 %a, i1 %cc) {435; CHECK-LABEL: @test_bits_sext(436; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 [[A:%.*]] to i32437; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -128438; CHECK-NEXT: ret i32 [[R]]439;440 %a.ext = sext i8 %a to i32441 %r = select i1 %cc, i32 %a.ext, i32 -128442 ret i32 %r443}444 445define i32 @test_bits_zext(i8 %a, i1 %cc) {446; CHECK-LABEL: @test_bits_zext(447; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A:%.*]] to i32448; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 255449; CHECK-NEXT: ret i32 [[R]]450;451 %a.ext = zext i8 %a to i32452 %r = select i1 %cc, i32 %a.ext, i32 255453 ret i32 %r454}455 456define i32 @sel_sext_const_uses(i8 %a, i8 %x) {457; CHECK-LABEL: @sel_sext_const_uses(458; CHECK-NEXT: [[COND:%.*]] = icmp ugt i8 [[X:%.*]], 15459; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 [[A:%.*]] to i32460; CHECK-NEXT: call void @use32(i32 [[A_EXT]])461; CHECK-NEXT: [[R:%.*]] = select i1 [[COND]], i32 [[A_EXT]], i32 127462; CHECK-NEXT: ret i32 [[R]]463;464 %cond = icmp ugt i8 %x, 15465 %a.ext = sext i8 %a to i32466 call void @use32(i32 %a.ext)467 %r = select i1 %cond, i32 %a.ext, i32 127468 ret i32 %r469}470 471define i32 @sel_zext_const_uses(i8 %a, i8 %x) {472; CHECK-LABEL: @sel_zext_const_uses(473; CHECK-NEXT: [[COND:%.*]] = icmp sgt i8 [[X:%.*]], 15474; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A:%.*]] to i32475; CHECK-NEXT: call void @use32(i32 [[A_EXT]])476; CHECK-NEXT: [[R:%.*]] = select i1 [[COND]], i32 255, i32 [[A_EXT]]477; CHECK-NEXT: ret i32 [[R]]478;479 %cond = icmp sgt i8 %x, 15480 %a.ext = zext i8 %a to i32481 call void @use32(i32 %a.ext)482 %r = select i1 %cond, i32 255, i32 %a.ext483 ret i32 %r484}485 486define i32 @test_op_op(i32 %a, i32 %b, i32 %c) {487; CHECK-LABEL: @test_op_op(488; CHECK-NEXT: [[CCC:%.*]] = icmp sgt i32 [[C:%.*]], 0489; CHECK-NEXT: [[R_V_V:%.*]] = select i1 [[CCC]], i32 [[A:%.*]], i32 [[B:%.*]]490; CHECK-NEXT: [[R_V:%.*]] = icmp sgt i32 [[R_V_V]], 0491; CHECK-NEXT: [[R:%.*]] = sext i1 [[R_V]] to i32492; CHECK-NEXT: ret i32 [[R]]493;494 %cca = icmp sgt i32 %a, 0495 %ccax = sext i1 %cca to i32496 %ccb = icmp sgt i32 %b, 0497 %ccbx = sext i1 %ccb to i32498 %ccc = icmp sgt i32 %c, 0499 %r = select i1 %ccc, i32 %ccax, i32 %ccbx500 ret i32 %r501}502 503define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) {504; CHECK-LABEL: @test_vectors_sext(505; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer506; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>507; CHECK-NEXT: ret <2 x i32> [[R]]508;509 %ccax = sext <2 x i1> %cca to <2 x i32>510 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>511 ret <2 x i32> %r512}513 514define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {515; CHECK-LABEL: @test_vectors_sext_nonsplat(516; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 false, i1 true>517; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>518; CHECK-NEXT: ret <2 x i32> [[R]]519;520 %ccax = sext <2 x i1> %cca to <2 x i32>521 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1>522 ret <2 x i32> %r523}524 525define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) {526; CHECK-LABEL: @test_vectors_zext(527; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer528; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>529; CHECK-NEXT: ret <2 x i32> [[R]]530;531 %ccax = zext <2 x i1> %cca to <2 x i32>532 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>533 ret <2 x i32> %r534}535 536define <2 x i32> @test_vectors_zext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {537; CHECK-LABEL: @test_vectors_zext_nonsplat(538; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 true, i1 false>539; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>540; CHECK-NEXT: ret <2 x i32> [[R]]541;542 %ccax = zext <2 x i1> %cca to <2 x i32>543 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 1, i32 0>544 ret <2 x i32> %r545}546 547define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {548; CHECK-LABEL: @scalar_select_of_vectors_sext(549; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer550; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>551; CHECK-NEXT: ret <2 x i32> [[R]]552;553 %ccax = sext <2 x i1> %cca to <2 x i32>554 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>555 ret <2 x i32> %r556}557 558define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) {559; CHECK-LABEL: @scalar_select_of_vectors_zext(560; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer561; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>562; CHECK-NEXT: ret <2 x i32> [[R]]563;564 %ccax = zext <2 x i1> %cca to <2 x i32>565 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>566 ret <2 x i32> %r567}568 569define i32 @sext_true_val_must_be_all_ones(i1 %x) {570; CHECK-LABEL: @sext_true_val_must_be_all_ones(571; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 -1, i32 42, !prof [[PROF0:![0-9]+]]572; CHECK-NEXT: ret i32 [[SEL]]573;574 %ext = sext i1 %x to i32575 %sel = select i1 %x, i32 %ext, i32 42, !prof !0576 ret i32 %sel577}578 579define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) {580; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec(581; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> splat (i32 -1), <2 x i32> <i32 42, i32 12>, !prof [[PROF0]]582; CHECK-NEXT: ret <2 x i32> [[SEL]]583;584 %ext = sext <2 x i1> %x to <2 x i32>585 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0586 ret <2 x i32> %sel587}588 589define i32 @zext_true_val_must_be_one(i1 %x) {590; CHECK-LABEL: @zext_true_val_must_be_one(591; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 1, i32 42, !prof [[PROF0]]592; CHECK-NEXT: ret i32 [[SEL]]593;594 %ext = zext i1 %x to i32595 %sel = select i1 %x, i32 %ext, i32 42, !prof !0596 ret i32 %sel597}598 599define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) {600; CHECK-LABEL: @zext_true_val_must_be_one_vec(601; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> splat (i32 1), <2 x i32> <i32 42, i32 12>, !prof [[PROF0]]602; CHECK-NEXT: ret <2 x i32> [[SEL]]603;604 %ext = zext <2 x i1> %x to <2 x i32>605 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0606 ret <2 x i32> %sel607}608 609define i32 @sext_false_val_must_be_zero(i1 %x) {610; CHECK-LABEL: @sext_false_val_must_be_zero(611; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof [[PROF0]]612; CHECK-NEXT: ret i32 [[SEL]]613;614 %ext = sext i1 %x to i32615 %sel = select i1 %x, i32 42, i32 %ext, !prof !0616 ret i32 %sel617}618 619define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) {620; CHECK-LABEL: @sext_false_val_must_be_zero_vec(621; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof [[PROF0]]622; CHECK-NEXT: ret <2 x i32> [[SEL]]623;624 %ext = sext <2 x i1> %x to <2 x i32>625 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0626 ret <2 x i32> %sel627}628 629define i32 @zext_false_val_must_be_zero(i1 %x) {630; CHECK-LABEL: @zext_false_val_must_be_zero(631; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof [[PROF0]]632; CHECK-NEXT: ret i32 [[SEL]]633;634 %ext = zext i1 %x to i32635 %sel = select i1 %x, i32 42, i32 %ext, !prof !0636 ret i32 %sel637}638 639define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) {640; CHECK-LABEL: @zext_false_val_must_be_zero_vec(641; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof [[PROF0]]642; CHECK-NEXT: ret <2 x i32> [[SEL]]643;644 %ext = zext <2 x i1> %x to <2 x i32>645 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0646 ret <2 x i32> %sel647}648 649!0 = !{!"branch_weights", i32 3, i32 5}650 651