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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) {5; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(6; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 27; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 608; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i649; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]10; CHECK-NEXT: ret i64 [[TMP4]]11;12 %1 = and i32 %x, 1513 %2 = shl nuw nsw i32 %1, 214 %3 = zext i32 %2 to i6415 %4 = icmp eq i32 %1, 016 %5 = ashr i64 %y, %317 %6 = select i1 %4, i64 %y, i64 %518 ret i64 %619}20 21define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) {22; CHECK-LABEL: @test_shl_nuw__all_are_safe(23; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 224; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 6025; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6426; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]27; CHECK-NEXT: ret i64 [[TMP4]]28;29 %1 = and i32 %x, 1530 %2 = shl nuw i32 %1, 231 %3 = zext i32 %2 to i6432 %4 = icmp eq i32 %1, 033 %5 = ashr i64 %y, %334 %6 = select i1 %4, i64 %y, i64 %535 ret i64 %636}37 38define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) {39; CHECK-LABEL: @test_shl_nsw__all_are_safe(40; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 241; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 6042; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6443; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]44; CHECK-NEXT: ret i64 [[TMP4]]45;46 %1 = and i32 %x, 1547 %2 = shl nsw i32 %1, 248 %3 = zext i32 %2 to i6449 %4 = icmp eq i32 %1, 050 %5 = ashr i64 %y, %351 %6 = select i1 %4, i64 %y, i64 %552 ret i64 %653}54 55define i64 @test_shl__all_are_safe(i32 %x, i64 %y) {56; CHECK-LABEL: @test_shl__all_are_safe(57; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 258; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 6059; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6460; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]61; CHECK-NEXT: ret i64 [[TMP4]]62;63 %1 = and i32 %x, 1564 %2 = shl i32 %1, 265 %3 = zext i32 %2 to i6466 %4 = icmp eq i32 %1, 067 %5 = ashr i64 %y, %368 %6 = select i1 %4, i64 %y, i64 %569 ret i64 %670}71 72define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {73; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(74; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 275; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -876; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6477; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]78; CHECK-NEXT: ret i64 [[TMP4]]79;80 %1 = and i32 %x, 107374182281 %2 = shl nuw nsw i32 %1, 282 %3 = zext i32 %2 to i6483 %4 = icmp eq i32 %1, 084 %5 = ashr i64 %y, %385 %6 = select i1 %4, i64 %y, i64 %586 ret i64 %687}88 89define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {90; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(91; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 292; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -893; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6494; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]95; CHECK-NEXT: ret i64 [[TMP4]]96;97 %1 = and i32 %x, 107374182298 %2 = shl nuw i32 %1, 299 %3 = zext i32 %2 to i64100 %4 = icmp eq i32 %1, 0101 %5 = ashr i64 %y, %3102 %6 = select i1 %4, i64 %y, i64 %5103 ret i64 %6104}105 106define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {107; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(108; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2109; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8110; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64111; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]112; CHECK-NEXT: ret i64 [[TMP4]]113;114 %1 = and i32 %x, 1073741822115 %2 = shl nsw i32 %1, 2116 %3 = zext i32 %2 to i64117 %4 = icmp eq i32 %1, 0118 %5 = ashr i64 %y, %3119 %6 = select i1 %4, i64 %y, i64 %5120 ret i64 %6121}122 123define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {124; CHECK-LABEL: @test_shl__nuw_is_safe(125; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2126; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8127; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64128; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]129; CHECK-NEXT: ret i64 [[TMP4]]130;131 %1 = and i32 %x, 1073741822132 %2 = shl i32 %1, 2133 %3 = zext i32 %2 to i64134 %4 = icmp eq i32 %1, 0135 %5 = ashr i64 %y, %3136 %6 = select i1 %4, i64 %y, i64 %5137 ret i64 %6138}139 140define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) {141; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe(142; CHECK-NEXT: ret i32 0143;144 %1 = or i32 %x, -83886080145 %2 = icmp eq i32 %1, -83886079146 %3 = shl nuw nsw i32 %1, 2147 %4 = select i1 %2, i32 -335544316, i32 %3148 %5 = mul i32 %4, %1149 %6 = mul i32 %5, %3150 ret i32 %6151}152 153define i32 @test_shl_nuw__nsw_is_safe(i32 %x) {154; CHECK-LABEL: @test_shl_nuw__nsw_is_safe(155; CHECK-NEXT: ret i32 0156;157 %1 = or i32 %x, -83886080158 %2 = icmp eq i32 %1, -83886079159 %3 = shl nuw i32 %1, 2160 %4 = select i1 %2, i32 -335544316, i32 %3161 %5 = mul i32 %4, %1162 %6 = mul i32 %5, %3163 ret i32 %6164}165 166define i32 @test_shl_nsw__nsw_is_safe(i32 %x) {167; CHECK-LABEL: @test_shl_nsw__nsw_is_safe(168; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080169; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2170; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]171; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]172; CHECK-NEXT: ret i32 [[TMP4]]173;174 %1 = or i32 %x, -83886080175 %2 = icmp eq i32 %1, -83886079176 %3 = shl nsw i32 %1, 2177 %4 = select i1 %2, i32 -335544316, i32 %3178 %5 = mul i32 %4, %1179 %6 = mul i32 %5, %3180 ret i32 %6181}182 183define i32 @test_shl__nsw_is_safe(i32 %x) {184; CHECK-LABEL: @test_shl__nsw_is_safe(185; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080186; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2187; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]188; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]189; CHECK-NEXT: ret i32 [[TMP4]]190;191 %1 = or i32 %x, -83886080192 %2 = icmp eq i32 %1, -83886079193 %3 = shl i32 %1, 2194 %4 = select i1 %2, i32 -335544316, i32 %3195 %5 = mul i32 %4, %1196 %6 = mul i32 %5, %3197 ret i32 %6198}199 200 201define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {202; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(203; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2204; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8205; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64206; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]207; CHECK-NEXT: ret i64 [[TMP4]]208;209 %1 = and i32 %x, 4294967294210 %2 = shl nuw nsw i32 %1, 2211 %3 = zext i32 %2 to i64212 %4 = icmp eq i32 %1, 0213 %5 = ashr i64 %y, %3214 %6 = select i1 %4, i64 %y, i64 %5215 ret i64 %6216}217 218define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {219; CHECK-LABEL: @test_shl_nuw__none_are_safe(220; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2221; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8222; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64223; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]224; CHECK-NEXT: ret i64 [[TMP4]]225;226 %1 = and i32 %x, 4294967294227 %2 = shl nuw i32 %1, 2228 %3 = zext i32 %2 to i64229 %4 = icmp eq i32 %1, 0230 %5 = ashr i64 %y, %3231 %6 = select i1 %4, i64 %y, i64 %5232 ret i64 %6233}234 235define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {236; CHECK-LABEL: @test_shl_nsw__none_are_safe(237; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2238; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8239; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64240; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]241; CHECK-NEXT: ret i64 [[TMP4]]242;243 %1 = and i32 %x, 4294967294244 %2 = shl nsw i32 %1, 2245 %3 = zext i32 %2 to i64246 %4 = icmp eq i32 %1, 0247 %5 = ashr i64 %y, %3248 %6 = select i1 %4, i64 %y, i64 %5249 ret i64 %6250}251 252define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {253; CHECK-LABEL: @test_shl__none_are_safe(254; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2255; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8256; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64257; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]258; CHECK-NEXT: ret i64 [[TMP4]]259;260 %1 = and i32 %x, 4294967294261 %2 = shl i32 %1, 2262 %3 = zext i32 %2 to i64263 %4 = icmp eq i32 %1, 0264 %5 = ashr i64 %y, %3265 %6 = select i1 %4, i64 %y, i64 %5266 ret i64 %6267}268 269define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) {270; CHECK-LABEL: @test_lshr_exact__exact_is_safe(271; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2272; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15273; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64274; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]275; CHECK-NEXT: ret i64 [[TMP4]]276;277 %1 = and i32 %x, 60278 %2 = lshr exact i32 %1, 2279 %3 = zext i32 %2 to i64280 %4 = icmp eq i32 %1, 0281 %5 = ashr i64 %y, %3282 %6 = select i1 %4, i64 %y, i64 %5283 ret i64 %6284}285 286define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) {287; CHECK-LABEL: @test_lshr__exact_is_safe(288; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2289; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15290; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64291; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]292; CHECK-NEXT: ret i64 [[TMP4]]293;294 %1 = and i32 %x, 60295 %2 = lshr i32 %1, 2296 %3 = zext i32 %2 to i64297 %4 = icmp eq i32 %1, 0298 %5 = ashr i64 %y, %3299 %6 = select i1 %4, i64 %y, i64 %5300 ret i64 %6301}302 303define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {304; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(305; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2306; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15307; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64308; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]309; CHECK-NEXT: ret i64 [[TMP4]]310;311 %1 = and i32 %x, 63312 %2 = lshr exact i32 %1, 2313 %3 = zext i32 %2 to i64314 %4 = icmp eq i32 %1, 0315 %5 = ashr i64 %y, %3316 %6 = select i1 %4, i64 %y, i64 %5317 ret i64 %6318}319 320define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) {321; CHECK-LABEL: @test_lshr__exact_is_unsafe(322; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2323; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15324; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64325; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]326; CHECK-NEXT: ret i64 [[TMP4]]327;328 %1 = and i32 %x, 63329 %2 = lshr i32 %1, 2330 %3 = zext i32 %2 to i64331 %4 = icmp eq i32 %1, 0332 %5 = ashr i64 %y, %3333 %6 = select i1 %4, i64 %y, i64 %5334 ret i64 %6335}336 337define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {338; CHECK-LABEL: @test_ashr_exact__exact_is_safe(339; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2340; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897341; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64342; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]343; CHECK-NEXT: ret i64 [[TMP4]]344;345 %1 = and i32 %x, -2147483588346 %2 = ashr exact i32 %1, 2347 %3 = zext i32 %2 to i64348 %4 = icmp eq i32 %1, 0349 %5 = ashr i64 %y, %3350 %6 = select i1 %4, i64 %y, i64 %5351 ret i64 %6352}353 354define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {355; CHECK-LABEL: @test_ashr__exact_is_safe(356; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2357; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897358; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64359; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]360; CHECK-NEXT: ret i64 [[TMP4]]361;362 %1 = and i32 %x, -2147483588363 %2 = ashr i32 %1, 2364 %3 = zext i32 %2 to i64365 %4 = icmp eq i32 %1, 0366 %5 = ashr i64 %y, %3367 %6 = select i1 %4, i64 %y, i64 %5368 ret i64 %6369}370 371define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {372; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(373; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2374; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897375; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64376; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]377; CHECK-NEXT: ret i64 [[TMP4]]378;379 %1 = and i32 %x, -2147483585380 %2 = ashr exact i32 %1, 2381 %3 = zext i32 %2 to i64382 %4 = icmp eq i32 %1, 0383 %5 = ashr i64 %y, %3384 %6 = select i1 %4, i64 %y, i64 %5385 ret i64 %6386}387 388define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {389; CHECK-LABEL: @test_ashr__exact_is_unsafe(390; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2391; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897392; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64393; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]394; CHECK-NEXT: ret i64 [[TMP4]]395;396 %1 = and i32 %x, -2147483585397 %2 = ashr i32 %1, 2398 %3 = zext i32 %2 to i64399 %4 = icmp eq i32 %1, 0400 %5 = ashr i64 %y, %3401 %6 = select i1 %4, i64 %y, i64 %5402 ret i64 %6403}404 405define i32 @test_add_nuw_nsw__all_are_safe(i32 %x) {406; CHECK-LABEL: @test_add_nuw_nsw__all_are_safe(407; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823408; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1409; CHECK-NEXT: ret i32 [[ADD]]410;411 %and = and i32 %x, 1073741823412 %cmp = icmp eq i32 %and, 3413 %add = add nuw nsw i32 %and, 1414 %sel = select i1 %cmp, i32 4, i32 %add415 ret i32 %sel416}417 418define i32 @test_add_nuw__all_are_safe(i32 %x) {419; CHECK-LABEL: @test_add_nuw__all_are_safe(420; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823421; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1422; CHECK-NEXT: ret i32 [[ADD]]423;424 %and = and i32 %x, 1073741823425 %cmp = icmp eq i32 %and, 3426 %add = add nuw i32 %and, 1427 %sel = select i1 %cmp, i32 4, i32 %add428 ret i32 %sel429}430 431define i32 @test_add_nsw__all_are_safe(i32 %x) {432; CHECK-LABEL: @test_add_nsw__all_are_safe(433; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823434; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1435; CHECK-NEXT: ret i32 [[ADD]]436;437 %and = and i32 %x, 1073741823438 %cmp = icmp eq i32 %and, 3439 %add = add nsw i32 %and, 1440 %sel = select i1 %cmp, i32 4, i32 %add441 ret i32 %sel442}443 444define i32 @test_add__all_are_safe(i32 %x) {445; CHECK-LABEL: @test_add__all_are_safe(446; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823447; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1448; CHECK-NEXT: ret i32 [[ADD]]449;450 %and = and i32 %x, 1073741823451 %cmp = icmp eq i32 %and, 3452 %add = add i32 %and, 1453 %sel = select i1 %cmp, i32 4, i32 %add454 ret i32 %sel455}456 457define i32 @test_add_nuw_nsw__nuw_is_safe(i32 %x) {458; CHECK-LABEL: @test_add_nuw_nsw__nuw_is_safe(459; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647460; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1461; CHECK-NEXT: ret i32 [[ADD]]462;463 %and = and i32 %x, 2147483647464 %cmp = icmp eq i32 %and, 2147483647465 %add = add nuw nsw i32 %and, 1466 %sel = select i1 %cmp, i32 -2147483648, i32 %add467 ret i32 %sel468}469 470define i32 @test_add_nuw__nuw_is_safe(i32 %x) {471; CHECK-LABEL: @test_add_nuw__nuw_is_safe(472; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647473; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1474; CHECK-NEXT: ret i32 [[ADD]]475;476 %and = and i32 %x, 2147483647477 %cmp = icmp eq i32 %and, 2147483647478 %add = add nuw i32 %and, 1479 %sel = select i1 %cmp, i32 -2147483648, i32 %add480 ret i32 %sel481}482 483define i32 @test_add_nsw__nuw_is_safe(i32 %x) {484; CHECK-LABEL: @test_add_nsw__nuw_is_safe(485; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647486; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1487; CHECK-NEXT: ret i32 [[ADD]]488;489 %and = and i32 %x, 2147483647490 %cmp = icmp eq i32 %and, 2147483647491 %add = add nsw i32 %and, 1492 %sel = select i1 %cmp, i32 -2147483648, i32 %add493 ret i32 %sel494}495 496define i32 @test_add__nuw_is_safe(i32 %x) {497; CHECK-LABEL: @test_add__nuw_is_safe(498; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647499; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1500; CHECK-NEXT: ret i32 [[ADD]]501;502 %and = and i32 %x, 2147483647503 %cmp = icmp eq i32 %and, 2147483647504 %add = add i32 %and, 1505 %sel = select i1 %cmp, i32 -2147483648, i32 %add506 ret i32 %sel507}508 509define i32 @test_add_nuw_nsw__nsw_is_safe(i32 %x) {510; CHECK-LABEL: @test_add_nuw_nsw__nsw_is_safe(511; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648512; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1513; CHECK-NEXT: ret i32 [[ADD]]514;515 %or = or i32 %x, -2147483648516 %cmp = icmp eq i32 %or, -1517 %add = add nuw nsw i32 %or, 1518 %sel = select i1 %cmp, i32 0, i32 %add519 ret i32 %sel520}521 522define i32 @test_add_nuw__nsw_is_safe(i32 %x) {523; CHECK-LABEL: @test_add_nuw__nsw_is_safe(524; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648525; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1526; CHECK-NEXT: ret i32 [[ADD]]527;528 %or = or i32 %x, -2147483648529 %cmp = icmp eq i32 %or, -1530 %add = add nuw i32 %or, 1531 %sel = select i1 %cmp, i32 0, i32 %add532 ret i32 %sel533}534 535define i32 @test_add_nsw__nsw_is_safe(i32 %x) {536; CHECK-LABEL: @test_add_nsw__nsw_is_safe(537; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648538; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1539; CHECK-NEXT: ret i32 [[ADD]]540;541 %or = or i32 %x, -2147483648542 %cmp = icmp eq i32 %or, -1543 %add = add nsw i32 %or, 1544 %sel = select i1 %cmp, i32 0, i32 %add545 ret i32 %sel546}547 548define i32 @test_add__nsw_is_safe(i32 %x) {549; CHECK-LABEL: @test_add__nsw_is_safe(550; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648551; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1552; CHECK-NEXT: ret i32 [[ADD]]553;554 %or = or i32 %x, -2147483648555 %cmp = icmp eq i32 %or, -1556 %add = add i32 %or, 1557 %sel = select i1 %cmp, i32 0, i32 %add558 ret i32 %sel559}560 561define i32 @test_add_nuw_nsw__none_are_safe(i32 %x) {562; CHECK-LABEL: @test_add_nuw_nsw__none_are_safe(563; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1564; CHECK-NEXT: ret i32 [[ADD]]565;566 %cmp = icmp eq i32 %x, 3567 %add = add nuw nsw i32 %x, 1568 %sel = select i1 %cmp, i32 4, i32 %add569 ret i32 %sel570}571 572define i32 @test_add_nuw__none_are_safe(i32 %x) {573; CHECK-LABEL: @test_add_nuw__none_are_safe(574; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1575; CHECK-NEXT: ret i32 [[ADD]]576;577 %cmp = icmp eq i32 %x, 3578 %add = add nuw i32 %x, 1579 %sel = select i1 %cmp, i32 4, i32 %add580 ret i32 %sel581}582 583define i32 @test_add_nsw__none_are_safe(i32 %x) {584; CHECK-LABEL: @test_add_nsw__none_are_safe(585; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1586; CHECK-NEXT: ret i32 [[ADD]]587;588 %cmp = icmp eq i32 %x, 3589 %add = add nsw i32 %x, 1590 %sel = select i1 %cmp, i32 4, i32 %add591 ret i32 %sel592}593 594define i32 @test_add__none_are_safe(i32 %x) {595; CHECK-LABEL: @test_add__none_are_safe(596; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1597; CHECK-NEXT: ret i32 [[ADD]]598;599 %cmp = icmp eq i32 %x, 3600 %add = add i32 %x, 1601 %sel = select i1 %cmp, i32 4, i32 %add602 ret i32 %sel603}604 605define i32 @test_sub_nuw_nsw__all_are_safe(i32 %x) {606; CHECK-LABEL: @test_sub_nuw_nsw__all_are_safe(607; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255608; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]609; CHECK-NEXT: ret i32 [[SUB]]610;611 %and = and i32 %x, 255612 %cmp = icmp eq i32 %and, 6613 %sub = sub nuw nsw i32 -254, %and614 %sel = select i1 %cmp, i32 -260, i32 %sub615 ret i32 %sel616}617 618define i32 @test_sub_nuw__all_are_safe(i32 %x) {619; CHECK-LABEL: @test_sub_nuw__all_are_safe(620; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255621; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]622; CHECK-NEXT: ret i32 [[SUB]]623;624 %and = and i32 %x, 255625 %cmp = icmp eq i32 %and, 6626 %sub = sub nuw i32 -254, %and627 %sel = select i1 %cmp, i32 -260, i32 %sub628 ret i32 %sel629}630 631define i32 @test_sub_nsw__all_are_safe(i32 %x) {632; CHECK-LABEL: @test_sub_nsw__all_are_safe(633; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255634; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]635; CHECK-NEXT: ret i32 [[SUB]]636;637 %and = and i32 %x, 255638 %cmp = icmp eq i32 %and, 6639 %sub = sub nsw i32 -254, %and640 %sel = select i1 %cmp, i32 -260, i32 %sub641 ret i32 %sel642}643 644define i32 @test_sub__all_are_safe(i32 %x) {645; CHECK-LABEL: @test_sub__all_are_safe(646; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255647; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]648; CHECK-NEXT: ret i32 [[SUB]]649;650 %and = and i32 %x, 255651 %cmp = icmp eq i32 %and, 6652 %sub = sub i32 -254, %and653 %sel = select i1 %cmp, i32 -260, i32 %sub654 ret i32 %sel655}656 657define i32 @test_sub_nuw_nsw__nuw_is_safe(i32 %x) {658; CHECK-LABEL: @test_sub_nuw_nsw__nuw_is_safe(659; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647660; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]661; CHECK-NEXT: ret i32 [[SUB]]662;663 %and = and i32 %x, 2147483647664 %cmp = icmp eq i32 %and, 1073741824665 %sub = sub nuw nsw i32 -2147483648, %and666 %sel = select i1 %cmp, i32 1073741824, i32 %sub667 ret i32 %sel668}669 670define i32 @test_sub_nuw__nuw_is_safe(i32 %x) {671; CHECK-LABEL: @test_sub_nuw__nuw_is_safe(672; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647673; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]674; CHECK-NEXT: ret i32 [[SUB]]675;676 %and = and i32 %x, 2147483647677 %cmp = icmp eq i32 %and, 1073741824678 %sub = sub nuw i32 -2147483648, %and679 %sel = select i1 %cmp, i32 1073741824, i32 %sub680 ret i32 %sel681}682 683define i32 @test_sub_nsw__nuw_is_safe(i32 %x) {684; CHECK-LABEL: @test_sub_nsw__nuw_is_safe(685; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647686; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]687; CHECK-NEXT: ret i32 [[SUB]]688;689 %and = and i32 %x, 2147483647690 %cmp = icmp eq i32 %and, 1073741824691 %sub = sub nsw i32 -2147483648, %and692 %sel = select i1 %cmp, i32 1073741824, i32 %sub693 ret i32 %sel694}695 696define i32 @test_sub__nuw_is_safe(i32 %x) {697; CHECK-LABEL: @test_sub__nuw_is_safe(698; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647699; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]700; CHECK-NEXT: ret i32 [[SUB]]701;702 %and = and i32 %x, 2147483647703 %cmp = icmp eq i32 %and, 1073741824704 %sub = sub i32 -2147483648, %and705 %sel = select i1 %cmp, i32 1073741824, i32 %sub706 ret i32 %sel707}708 709define i32 @test_sub_nuw_nsw__nsw_is_safe(i32 %x) {710; CHECK-LABEL: @test_sub_nuw_nsw__nsw_is_safe(711; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648712; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]713; CHECK-NEXT: ret i32 [[SUB]]714;715 %or = or i32 %x, -2147483648716 %cmp = icmp eq i32 %or, -2147483647717 %sub = sub nuw nsw i32 -2147483648, %or718 %sel = select i1 %cmp, i32 -1, i32 %sub719 ret i32 %sel720}721 722define i32 @test_sub_nuw__nsw_is_safe(i32 %x) {723; CHECK-LABEL: @test_sub_nuw__nsw_is_safe(724; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648725; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]726; CHECK-NEXT: ret i32 [[SUB]]727;728 %or = or i32 %x, -2147483648729 %cmp = icmp eq i32 %or, -2147483647730 %sub = sub nuw i32 -2147483648, %or731 %sel = select i1 %cmp, i32 -1, i32 %sub732 ret i32 %sel733}734 735define i32 @test_sub_nsw__nsw_is_safe(i32 %x) {736; CHECK-LABEL: @test_sub_nsw__nsw_is_safe(737; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648738; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]739; CHECK-NEXT: ret i32 [[SUB]]740;741 %or = or i32 %x, -2147483648742 %cmp = icmp eq i32 %or, -2147483647743 %sub = sub nsw i32 -2147483648, %or744 %sel = select i1 %cmp, i32 -1, i32 %sub745 ret i32 %sel746}747 748define i32 @test_sub__nsw_is_safe(i32 %x) {749; CHECK-LABEL: @test_sub__nsw_is_safe(750; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648751; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]752; CHECK-NEXT: ret i32 [[SUB]]753;754 %or = or i32 %x, -2147483648755 %cmp = icmp eq i32 %or, -2147483647756 %sub = sub i32 -2147483648, %or757 %sel = select i1 %cmp, i32 -1, i32 %sub758 ret i32 %sel759}760 761define i32 @test_sub_nuw_nsw__none_are_safe(i32 %x) {762; CHECK-LABEL: @test_sub_nuw_nsw__none_are_safe(763; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]764; CHECK-NEXT: ret i32 [[SUB]]765;766 %cmp = icmp eq i32 %x, 1767 %sub = sub nuw nsw i32 -2147483648, %x768 %sel = select i1 %cmp, i32 2147483647, i32 %sub769 ret i32 %sel770}771 772define i32 @test_sub_nuw__none_are_safe(i32 %x) {773; CHECK-LABEL: @test_sub_nuw__none_are_safe(774; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]775; CHECK-NEXT: ret i32 [[SUB]]776;777 %cmp = icmp eq i32 %x, 1778 %sub = sub nuw i32 -2147483648, %x779 %sel = select i1 %cmp, i32 2147483647, i32 %sub780 ret i32 %sel781}782 783define i32 @test_sub_nsw__none_are_safe(i32 %x) {784; CHECK-LABEL: @test_sub_nsw__none_are_safe(785; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]786; CHECK-NEXT: ret i32 [[SUB]]787;788 %cmp = icmp eq i32 %x, 1789 %sub = sub nsw i32 -2147483648, %x790 %sel = select i1 %cmp, i32 2147483647, i32 %sub791 ret i32 %sel792}793 794define i32 @test_sub__none_are_safe(i32 %x) {795; CHECK-LABEL: @test_sub__none_are_safe(796; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]797; CHECK-NEXT: ret i32 [[SUB]]798;799 %cmp = icmp eq i32 %x, 1800 %sub = sub i32 -2147483648, %x801 %sel = select i1 %cmp, i32 2147483647, i32 %sub802 ret i32 %sel803}804 805define i32 @test_mul_nuw_nsw__all_are_safe(i32 %x) {806; CHECK-LABEL: @test_mul_nuw_nsw__all_are_safe(807; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255808; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9809; CHECK-NEXT: ret i32 [[MUL]]810;811 %and = and i32 %x, 255812 %cmp = icmp eq i32 %and, 17813 %mul = mul nuw nsw i32 %and, 9814 %sel = select i1 %cmp, i32 153, i32 %mul815 ret i32 %sel816}817 818define i32 @test_mul_nuw__all_are_safe(i32 %x) {819; CHECK-LABEL: @test_mul_nuw__all_are_safe(820; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255821; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9822; CHECK-NEXT: ret i32 [[MUL]]823;824 %and = and i32 %x, 255825 %cmp = icmp eq i32 %and, 17826 %mul = mul nuw i32 %and, 9827 %sel = select i1 %cmp, i32 153, i32 %mul828 ret i32 %sel829}830 831define i32 @test_mul_nsw__all_are_safe(i32 %x) {832; CHECK-LABEL: @test_mul_nsw__all_are_safe(833; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255834; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9835; CHECK-NEXT: ret i32 [[MUL]]836;837 %and = and i32 %x, 255838 %cmp = icmp eq i32 %and, 17839 %mul = mul nsw i32 %and, 9840 %sel = select i1 %cmp, i32 153, i32 %mul841 ret i32 %sel842}843 844define i32 @test_mul__all_are_safe(i32 %x) {845; CHECK-LABEL: @test_mul__all_are_safe(846; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255847; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9848; CHECK-NEXT: ret i32 [[MUL]]849;850 %and = and i32 %x, 255851 %cmp = icmp eq i32 %and, 17852 %mul = mul i32 %and, 9853 %sel = select i1 %cmp, i32 153, i32 %mul854 ret i32 %sel855}856 857define i32 @test_mul_nuw_nsw__nuw_is_safe(i32 %x) {858; CHECK-LABEL: @test_mul_nuw_nsw__nuw_is_safe(859; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457860; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9861; CHECK-NEXT: ret i32 [[MUL]]862;863 %and = and i32 %x, 268435457864 %cmp = icmp eq i32 %and, 268435456865 %mul = mul nuw nsw i32 %and, 9866 %sel = select i1 %cmp, i32 -1879048192, i32 %mul867 ret i32 %sel868}869 870define i32 @test_mul_nuw__nuw_is_safe(i32 %x) {871; CHECK-LABEL: @test_mul_nuw__nuw_is_safe(872; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457873; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9874; CHECK-NEXT: ret i32 [[MUL]]875;876 %and = and i32 %x, 268435457877 %cmp = icmp eq i32 %and, 268435456878 %mul = mul nuw i32 %and, 9879 %sel = select i1 %cmp, i32 -1879048192, i32 %mul880 ret i32 %sel881}882 883define i32 @test_mul_nsw__nuw_is_safe(i32 %x) {884; CHECK-LABEL: @test_mul_nsw__nuw_is_safe(885; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457886; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9887; CHECK-NEXT: ret i32 [[MUL]]888;889 %and = and i32 %x, 268435457890 %cmp = icmp eq i32 %and, 268435456891 %mul = mul nsw i32 %and, 9892 %sel = select i1 %cmp, i32 -1879048192, i32 %mul893 ret i32 %sel894}895 896define i32 @test_mul__nuw_is_safe(i32 %x) {897; CHECK-LABEL: @test_mul__nuw_is_safe(898; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457899; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9900; CHECK-NEXT: ret i32 [[MUL]]901;902 %and = and i32 %x, 268435457903 %cmp = icmp eq i32 %and, 268435456904 %mul = mul i32 %and, 9905 %sel = select i1 %cmp, i32 -1879048192, i32 %mul906 ret i32 %sel907}908 909define i32 @test_mul_nuw_nsw__nsw_is_safe(i32 %x) {910; CHECK-LABEL: @test_mul_nuw_nsw__nsw_is_safe(911; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080912; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9913; CHECK-NEXT: ret i32 [[MUL]]914;915 %and = or i32 %x, -83886080916 %cmp = icmp eq i32 %and, -83886079917 %mul = mul nuw nsw i32 %and, 9918 %sel = select i1 %cmp, i32 -754974711, i32 %mul919 ret i32 %sel920}921 922define i32 @test_mul_nuw__nsw_is_safe(i32 %x) {923; CHECK-LABEL: @test_mul_nuw__nsw_is_safe(924; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080925; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9926; CHECK-NEXT: ret i32 [[MUL]]927;928 %and = or i32 %x, -83886080929 %cmp = icmp eq i32 %and, -83886079930 %mul = mul nuw i32 %and, 9931 %sel = select i1 %cmp, i32 -754974711, i32 %mul932 ret i32 %sel933}934 935define i32 @test_mul_nsw__nsw_is_safe(i32 %x) {936; CHECK-LABEL: @test_mul_nsw__nsw_is_safe(937; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080938; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9939; CHECK-NEXT: ret i32 [[MUL]]940;941 %and = or i32 %x, -83886080942 %cmp = icmp eq i32 %and, -83886079943 %mul = mul nsw i32 %and, 9944 %sel = select i1 %cmp, i32 -754974711, i32 %mul945 ret i32 %sel946}947 948define i32 @test_mul__nsw_is_safe(i32 %x) {949; CHECK-LABEL: @test_mul__nsw_is_safe(950; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080951; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9952; CHECK-NEXT: ret i32 [[MUL]]953;954 %and = or i32 %x, -83886080955 %cmp = icmp eq i32 %and, -83886079956 %mul = mul i32 %and, 9957 %sel = select i1 %cmp, i32 -754974711, i32 %mul958 ret i32 %sel959}960 961define i32 @test_mul_nuw_nsw__none_are_safe(i32 %x) {962; CHECK-LABEL: @test_mul_nuw_nsw__none_are_safe(963; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9964; CHECK-NEXT: ret i32 [[MUL]]965;966 %cmp = icmp eq i32 %x, 805306368967 %mul = mul nuw nsw i32 %x, 9968 %sel = select i1 %cmp, i32 -1342177280, i32 %mul969 ret i32 %sel970}971 972define i32 @test_mul_nuw__none_are_safe(i32 %x) {973; CHECK-LABEL: @test_mul_nuw__none_are_safe(974; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9975; CHECK-NEXT: ret i32 [[MUL]]976;977 %cmp = icmp eq i32 %x, 805306368978 %mul = mul nuw i32 %x, 9979 %sel = select i1 %cmp, i32 -1342177280, i32 %mul980 ret i32 %sel981}982 983define i32 @test_mul_nsw__none_are_safe(i32 %x) {984; CHECK-LABEL: @test_mul_nsw__none_are_safe(985; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9986; CHECK-NEXT: ret i32 [[MUL]]987;988 %cmp = icmp eq i32 %x, 805306368989 %mul = mul nsw i32 %x, 9990 %sel = select i1 %cmp, i32 -1342177280, i32 %mul991 ret i32 %sel992}993 994define i32 @test_mul__none_are_safe(i32 %x) {995; CHECK-LABEL: @test_mul__none_are_safe(996; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9997; CHECK-NEXT: ret i32 [[MUL]]998;999 %cmp = icmp eq i32 %x, 8053063681000 %mul = mul i32 %x, 91001 %sel = select i1 %cmp, i32 -1342177280, i32 %mul1002 ret i32 %sel1003}1004