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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4; Given pattern:5; icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 06; we should move shifts to the same hand of 'and', i.e. e.g. rewrite as7; icmp eq/ne (and (((x shift Q) shift K), y)), 08; We are only interested in opposite logical shifts here.9; We still can handle the case where there is a truncation between a shift10; and an 'and', thought the legality check isn't obvious.11 12;-------------------------------------------------------------------------------13; Basic scalar tests14;-------------------------------------------------------------------------------15 16; This fold can't be performed for fully variable %x and %y17define i1 @n0(i32 %x, i64 %y, i32 %len) {18; CHECK-LABEL: @n0(19; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]20; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]21; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1622; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i6423; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]24; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i3225; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]26; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 027; CHECK-NEXT: ret i1 [[T5]]28;29 %t0 = sub i32 32, %len30 %t1 = shl i32 %x, %t031 %t2 = add i32 %len, -1632 %t2_wide = zext i32 %t2 to i6433 %t3 = lshr i64 %y, %t2_wide34 %t3_trunc = trunc i64 %t3 to i3235 %t4 = and i32 %t1, %t3_trunc36 %t5 = icmp ne i32 %t4, 037 ret i1 %t538}39 40; However we can fold if %x/%y are constants that pass extra legality check.41 42; New shift amount would be 16, %x has 16 leading zeros - can fold.43define i1 @t1(i64 %y, i32 %len) {44; CHECK-LABEL: @t1(45; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 429490176046; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 047; CHECK-NEXT: ret i1 [[T5]]48;49 %t0 = sub i32 32, %len50 %t1 = shl i32 65535, %t051 %t2 = add i32 %len, -1652 %t2_wide = zext i32 %t2 to i6453 %t3 = lshr i64 %y, %t2_wide54 %t3_trunc = trunc i64 %t3 to i3255 %t4 = and i32 %t1, %t3_trunc56 %t5 = icmp ne i32 %t4, 057 ret i1 %t558}59; Note that we indeed look at leading zeros!60define i1 @t1_single_bit(i64 %y, i32 %len) {61; CHECK-LABEL: @t1_single_bit(62; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 214748364863; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 064; CHECK-NEXT: ret i1 [[T5]]65;66 %t0 = sub i32 32, %len67 %t1 = shl i32 32768, %t068 %t2 = add i32 %len, -1669 %t2_wide = zext i32 %t2 to i6470 %t3 = lshr i64 %y, %t2_wide71 %t3_trunc = trunc i64 %t3 to i3272 %t4 = and i32 %t1, %t3_trunc73 %t5 = icmp ne i32 %t4, 074 ret i1 %t575}76; New shift amount would be 16, %x has 15 leading zeros - can not fold.77define i1 @n2(i64 %y, i32 %len) {78; CHECK-LABEL: @n2(79; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]80; CHECK-NEXT: [[T1:%.*]] = shl i32 131071, [[T0]]81; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1682; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i6483; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]84; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i3285; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]86; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 087; CHECK-NEXT: ret i1 [[T5]]88;89 %t0 = sub i32 32, %len90 %t1 = shl i32 131071, %t091 %t2 = add i32 %len, -1692 %t2_wide = zext i32 %t2 to i6493 %t3 = lshr i64 %y, %t2_wide94 %t3_trunc = trunc i64 %t3 to i3295 %t4 = and i32 %t1, %t3_trunc96 %t5 = icmp ne i32 %t4, 097 ret i1 %t598}99 100; New shift amount would be 16, %y has 47 leading zeros - can fold.101define i1 @t3(i32 %x, i32 %len) {102; CHECK-LABEL: @t3(103; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1104; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0105; CHECK-NEXT: ret i1 [[T5]]106;107 %t0 = sub i32 32, %len108 %t1 = shl i32 %x, %t0109 %t2 = add i32 %len, -16110 %t2_wide = zext i32 %t2 to i64111 %t3 = lshr i64 131071, %t2_wide112 %t3_trunc = trunc i64 %t3 to i32113 %t4 = and i32 %t1, %t3_trunc114 %t5 = icmp ne i32 %t4, 0115 ret i1 %t5116}117; Note that we indeed look at leading zeros!118define i1 @t3_singlebit(i32 %x, i32 %len) {119; CHECK-LABEL: @t3_singlebit(120; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1121; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0122; CHECK-NEXT: ret i1 [[T5]]123;124 %t0 = sub i32 32, %len125 %t1 = shl i32 %x, %t0126 %t2 = add i32 %len, -16127 %t2_wide = zext i32 %t2 to i64128 %t3 = lshr i64 65536, %t2_wide129 %t3_trunc = trunc i64 %t3 to i32130 %t4 = and i32 %t1, %t3_trunc131 %t5 = icmp ne i32 %t4, 0132 ret i1 %t5133}134; New shift amount would be 16, %y has 48 leading zeros - can not fold.135define i1 @n4(i32 %x, i32 %len) {136; CHECK-LABEL: @n4(137; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]138; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]139; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16140; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64141; CHECK-NEXT: [[T3:%.*]] = lshr i64 262143, [[T2_WIDE]]142; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc nuw nsw i64 [[T3]] to i32143; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]144; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0145; CHECK-NEXT: ret i1 [[T5]]146;147 %t0 = sub i32 32, %len148 %t1 = shl i32 %x, %t0149 %t2 = add i32 %len, -16150 %t2_wide = zext i32 %t2 to i64151 %t3 = lshr i64 262143, %t2_wide152 %t3_trunc = trunc i64 %t3 to i32153 %t4 = and i32 %t1, %t3_trunc154 %t5 = icmp ne i32 %t4, 0155 ret i1 %t5156}157 158; While we could still deal with arbitrary values if KnownBits can answer159; the question, it isn't obvious it's worth it, so let's not for now.160 161;-------------------------------------------------------------------------------162; Vector tests163;-------------------------------------------------------------------------------164 165; New shift amount would be 16, minimal count of leading zeros in %x is 16. Ok.166define <2 x i1> @t5_vec(<2 x i64> %y, <2 x i32> %len) {167; CHECK-LABEL: @t5_vec(168; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[Y:%.*]], splat (i64 16)169; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP1]], <i64 65535, i64 32767>170; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer171; CHECK-NEXT: ret <2 x i1> [[T5]]172;173 %t0 = sub <2 x i32> <i32 32, i32 32>, %len174 %t1 = shl <2 x i32> <i32 65535, i32 32767>, %t0175 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>176 %t2_wide = zext <2 x i32> %t2 to <2 x i64>177 %t3 = lshr <2 x i64> %y, %t2_wide178 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>179 %t4 = and <2 x i32> %t1, %t3_trunc180 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>181 ret <2 x i1> %t5182}183; New shift amount would be 16, minimal count of leading zeros in %x is 15, not ok to fold.184define <2 x i1> @n6_vec(<2 x i64> %y, <2 x i32> %len) {185; CHECK-LABEL: @n6_vec(186; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> splat (i32 32), [[LEN:%.*]]187; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> <i32 65535, i32 131071>, [[T0]]188; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], splat (i32 -16)189; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>190; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]191; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>192; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]193; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[T4]], zeroinitializer194; CHECK-NEXT: ret <2 x i1> [[T5]]195;196 %t0 = sub <2 x i32> <i32 32, i32 32>, %len197 %t1 = shl <2 x i32> <i32 65535, i32 131071>, %t0198 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>199 %t2_wide = zext <2 x i32> %t2 to <2 x i64>200 %t3 = lshr <2 x i64> %y, %t2_wide201 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>202 %t4 = and <2 x i32> %t1, %t3_trunc203 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>204 ret <2 x i1> %t5205}206 207; New shift amount would be 16, minimal count of leading zeros in %x is 47. Ok.208define <2 x i1> @t7_vec(<2 x i32> %x, <2 x i32> %len) {209; CHECK-LABEL: @t7_vec(210; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 0>211; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer212; CHECK-NEXT: ret <2 x i1> [[T5]]213;214 %t0 = sub <2 x i32> <i32 32, i32 32>, %len215 %t1 = shl <2 x i32> %x, %t0216 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>217 %t2_wide = zext <2 x i32> %t2 to <2 x i64>218 %t3 = lshr <2 x i64> <i64 131071, i64 65535>, %t2_wide219 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>220 %t4 = and <2 x i32> %t1, %t3_trunc221 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>222 ret <2 x i1> %t5223}224; New shift amount would be 16, minimal count of leading zeros in %x is 48, not ok to fold.225define <2 x i1> @n8_vec(<2 x i32> %x, <2 x i32> %len) {226; CHECK-LABEL: @n8_vec(227; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> splat (i32 32), [[LEN:%.*]]228; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]229; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], splat (i32 -16)230; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>231; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> <i64 131071, i64 262143>, [[T2_WIDE]]232; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc nuw nsw <2 x i64> [[T3]] to <2 x i32>233; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]234; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[T4]], zeroinitializer235; CHECK-NEXT: ret <2 x i1> [[T5]]236;237 %t0 = sub <2 x i32> <i32 32, i32 32>, %len238 %t1 = shl <2 x i32> %x, %t0239 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>240 %t2_wide = zext <2 x i32> %t2 to <2 x i64>241 %t3 = lshr <2 x i64> <i64 131071, i64 262143>, %t2_wide242 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>243 %t4 = and <2 x i32> %t1, %t3_trunc244 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>245 ret <2 x i1> %t5246}247 248;-------------------------------------------------------------------------------249 250; Ok if the final shift amount is exactly one less than widest bit width.251define i1 @t9_highest_bit(i32 %x, i64 %y, i32 %len) {252; CHECK-LABEL: @t9_highest_bit(253; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64254; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[Y:%.*]], 63255; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[TMP1]]256; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0257; CHECK-NEXT: ret i1 [[T5]]258;259 %t0 = sub i32 64, %len260 %t1 = shl i32 %x, %t0261 %t2 = add i32 %len, -1262 %t2_wide = zext i32 %t2 to i64263 %t3 = lshr i64 %y, %t2_wide264 %t3_trunc = trunc i64 %t3 to i32265 %t4 = and i32 %t1, %t3_trunc266 %t5 = icmp ne i32 %t4, 0267 ret i1 %t5268}269; Not highest bit.270define i1 @t10_almost_highest_bit(i32 %x, i64 %y, i32 %len) {271; CHECK-LABEL: @t10_almost_highest_bit(272; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]273; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]274; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -2275; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64276; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]277; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32278; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]279; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0280; CHECK-NEXT: ret i1 [[T5]]281;282 %t0 = sub i32 64, %len283 %t1 = shl i32 %x, %t0284 %t2 = add i32 %len, -2285 %t2_wide = zext i32 %t2 to i64286 %t3 = lshr i64 %y, %t2_wide287 %t3_trunc = trunc i64 %t3 to i32288 %t4 = and i32 %t1, %t3_trunc289 %t5 = icmp ne i32 %t4, 0290 ret i1 %t5291}292 293; Ok if the final shift amount is zero.294define i1 @t11_no_shift(i32 %x, i64 %y, i32 %len) {295; CHECK-LABEL: @t11_no_shift(296; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64297; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[Y:%.*]], [[TMP1]]298; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP2]], 0299; CHECK-NEXT: ret i1 [[T5]]300;301 %t0 = sub i32 64, %len302 %t1 = shl i32 %x, %t0303 %t2 = add i32 %len, -64304 %t2_wide = zext i32 %t2 to i64305 %t3 = lshr i64 %y, %t2_wide306 %t3_trunc = trunc i64 %t3 to i32307 %t4 = and i32 %t1, %t3_trunc308 %t5 = icmp ne i32 %t4, 0309 ret i1 %t5310}311; Not zero-shift.312define i1 @t10_shift_by_one(i32 %x, i64 %y, i32 %len) {313; CHECK-LABEL: @t10_shift_by_one(314; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]315; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]316; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -63317; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64318; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]319; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32320; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]321; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0322; CHECK-NEXT: ret i1 [[T5]]323;324 %t0 = sub i32 64, %len325 %t1 = shl i32 %x, %t0326 %t2 = add i32 %len, -63327 %t2_wide = zext i32 %t2 to i64328 %t3 = lshr i64 %y, %t2_wide329 %t3_trunc = trunc i64 %t3 to i32330 %t4 = and i32 %t1, %t3_trunc331 %t5 = icmp ne i32 %t4, 0332 ret i1 %t5333}334 335; A mix of those conditions is ok.336define <2 x i1> @t11_zero_and_almost_bitwidth(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {337; CHECK-LABEL: @t11_zero_and_almost_bitwidth(338; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> splat (i32 64), [[LEN:%.*]]339; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]340; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -1, i32 -64>341; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>342; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]343; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>344; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]345; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[T4]], zeroinitializer346; CHECK-NEXT: ret <2 x i1> [[T5]]347;348 %t0 = sub <2 x i32> <i32 64, i32 64>, %len349 %t1 = shl <2 x i32> %x, %t0350 %t2 = add <2 x i32> %len, <i32 -1, i32 -64>351 %t2_wide = zext <2 x i32> %t2 to <2 x i64>352 %t3 = lshr <2 x i64> %y, %t2_wide353 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>354 %t4 = and <2 x i32> %t1, %t3_trunc355 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>356 ret <2 x i1> %t5357}358define <2 x i1> @n12_bad(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {359; CHECK-LABEL: @n12_bad(360; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> splat (i32 64), [[LEN:%.*]]361; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]362; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -2, i32 -64>363; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>364; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]365; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>366; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]367; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[T4]], zeroinitializer368; CHECK-NEXT: ret <2 x i1> [[T5]]369;370 %t0 = sub <2 x i32> <i32 64, i32 64>, %len371 %t1 = shl <2 x i32> %x, %t0372 %t2 = add <2 x i32> %len, <i32 -2, i32 -64>373 %t2_wide = zext <2 x i32> %t2 to <2 x i64>374 %t3 = lshr <2 x i64> %y, %t2_wide375 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>376 %t4 = and <2 x i32> %t1, %t3_trunc377 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>378 ret <2 x i1> %t5379}380 381;------------------------------------------------------------------------------;382 383; Ok if one of the values being shifted is 1384define i1 @t13_x_is_one(i64 %y, i32 %len) {385; CHECK-LABEL: @t13_x_is_one(386; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 65536387; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0388; CHECK-NEXT: ret i1 [[T5]]389;390 %t0 = sub i32 32, %len391 %t1 = shl i32 1, %t0392 %t2 = add i32 %len, -16393 %t2_wide = zext i32 %t2 to i64394 %t3 = lshr i64 %y, %t2_wide395 %t3_trunc = trunc i64 %t3 to i32396 %t4 = and i32 %t1, %t3_trunc397 %t5 = icmp ne i32 %t4, 0398 ret i1 %t5399}400define i1 @t14_x_is_one(i32 %x, i32 %len) {401; CHECK-LABEL: @t14_x_is_one(402; CHECK-NEXT: ret i1 false403;404 %t0 = sub i32 32, %len405 %t1 = shl i32 %x, %t0406 %t2 = add i32 %len, -16407 %t2_wide = zext i32 %t2 to i64408 %t3 = lshr i64 1, %t2_wide409 %t3_trunc = trunc i64 %t3 to i32410 %t4 = and i32 %t1, %t3_trunc411 %t5 = icmp ne i32 %t4, 0412 ret i1 %t5413}414 415define <2 x i1> @t15_vec_x_is_one_or_zero(<2 x i64> %y, <2 x i32> %len) {416; CHECK-LABEL: @t15_vec_x_is_one_or_zero(417; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[Y:%.*]], splat (i64 48)418; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP1]], <i64 1, i64 0>419; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer420; CHECK-NEXT: ret <2 x i1> [[T5]]421;422 %t0 = sub <2 x i32> <i32 64, i32 64>, %len423 %t1 = shl <2 x i32> <i32 1, i32 0>, %t0424 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>425 %t2_wide = zext <2 x i32> %t2 to <2 x i64>426 %t3 = lshr <2 x i64> %y, %t2_wide427 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>428 %t4 = and <2 x i32> %t1, %t3_trunc429 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>430 ret <2 x i1> %t5431}432define <2 x i1> @t16_vec_y_is_one_or_zero(<2 x i32> %x, <2 x i32> %len) {433; CHECK-LABEL: @t16_vec_y_is_one_or_zero(434; CHECK-NEXT: ret <2 x i1> zeroinitializer435;436 %t0 = sub <2 x i32> <i32 64, i32 64>, %len437 %t1 = shl <2 x i32> %x, %t0438 %t2 = add <2 x i32> %len, <i32 -16, i32 -16>439 %t2_wide = zext <2 x i32> %t2 to <2 x i64>440 %t3 = lshr <2 x i64> <i64 1, i64 0>, %t2_wide441 %t3_trunc = trunc <2 x i64> %t3 to <2 x i32>442 %t4 = and <2 x i32> %t1, %t3_trunc443 %t5 = icmp ne <2 x i32> %t4, <i32 0, i32 0>444 ret <2 x i1> %t5445}446 447;------------------------------------------------------------------------------;448 449; All other tests - extra uses, etc are already covered in450; shift-amount-reassociation-in-bittest-with-truncation-shl.ll and451; shift-amount-reassociation-in-bittest.ll452 453; And that's the main motivational pattern:454define i1 @rawspeed_signbit(i64 %storage, i32 %nbits) {455; CHECK-LABEL: @rawspeed_signbit(456; CHECK-NEXT: [[ISBITUNSET:%.*]] = icmp sgt i64 [[STORAGE:%.*]], -1457; CHECK-NEXT: ret i1 [[ISBITUNSET]]458;459 %skipnbits = sub nsw i32 64, %nbits460 %skipnbitswide = zext i32 %skipnbits to i64461 %datawide = lshr i64 %storage, %skipnbitswide462 %data = trunc i64 %datawide to i32463 %nbitsminusone = add nsw i32 %nbits, -1464 %bitmask = shl i32 1, %nbitsminusone465 %bitmasked = and i32 %bitmask, %data466 %isbitunset = icmp eq i32 %bitmasked, 0467 ret i1 %isbitunset468}469