279 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4target datalayout = "n8:16:32"5 6; Given pattern:7; (trunc (x << Q) to iDst) << K8; we should rewrite it as9; (trunc (x << (Q+K)) to iDst) iff (Q+K) u< iDst10; This is only valid for shl.11; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!12 13; Basic scalar test14 15define i16 @t0(i32 %x, i16 %y) {16; CHECK-LABEL: @t0(17; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i1618; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 819; CHECK-NEXT: ret i16 [[T5]]20;21 %t0 = sub i16 32, %y22 %t1 = zext i16 %t0 to i3223 %t2 = shl i32 %x, %t124 %t3 = trunc i32 %t2 to i1625 %t4 = add i16 %y, -2426 %t5 = shl i16 %t3, %t427 ret i16 %t528}29 30define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {31; CHECK-LABEL: @t1_vec_splat(32; CHECK-NEXT: [[X_TR:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i16>33; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[X_TR]], splat (i16 8)34; CHECK-NEXT: ret <2 x i16> [[T5]]35;36 %t0 = sub <2 x i16> <i16 32, i16 32>, %y37 %t1 = zext <2 x i16> %t0 to <2 x i32>38 %t2 = shl <2 x i32> %x, %t139 %t3 = trunc <2 x i32> %t2 to <2 x i16>40 %t4 = add <2 x i16> %y, <i16 -24, i16 -24>41 %t5 = shl <2 x i16> %t3, %t442 ret <2 x i16> %t543}44 45define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {46; CHECK-LABEL: @t2_vec_nonsplat(47; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>48; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>49; CHECK-NEXT: ret <2 x i16> [[T5]]50;51 %t0 = sub <2 x i16> <i16 32, i16 30>, %y52 %t1 = zext <2 x i16> %t0 to <2 x i32>53 %t2 = shl <2 x i32> %x, %t154 %t3 = trunc <2 x i32> %t2 to <2 x i16>55 %t4 = add <2 x i16> %y, <i16 -24, i16 0>56 %t5 = shl <2 x i16> %t3, %t457 ret <2 x i16> %t558}59 60; Basic vector tests61 62define <3 x i16> @t3_vec_nonsplat_poison0(<3 x i32> %x, <3 x i16> %y) {63; CHECK-LABEL: @t3_vec_nonsplat_poison0(64; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>65; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>66; CHECK-NEXT: ret <3 x i16> [[T5]]67;68 %t0 = sub <3 x i16> <i16 32, i16 poison, i16 32>, %y69 %t1 = zext <3 x i16> %t0 to <3 x i32>70 %t2 = shl <3 x i32> %x, %t171 %t3 = trunc <3 x i32> %t2 to <3 x i16>72 %t4 = add <3 x i16> %y, <i16 -24, i16 -24, i16 -24>73 %t5 = shl <3 x i16> %t3, %t474 ret <3 x i16> %t575}76 77define <3 x i16> @t4_vec_nonsplat_poison1(<3 x i32> %x, <3 x i16> %y) {78; CHECK-LABEL: @t4_vec_nonsplat_poison1(79; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>80; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>81; CHECK-NEXT: ret <3 x i16> [[T5]]82;83 %t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y84 %t1 = zext <3 x i16> %t0 to <3 x i32>85 %t2 = shl <3 x i32> %x, %t186 %t3 = trunc <3 x i32> %t2 to <3 x i16>87 %t4 = add <3 x i16> %y, <i16 -24, i16 poison, i16 -24>88 %t5 = shl <3 x i16> %t3, %t489 ret <3 x i16> %t590}91 92define <3 x i16> @t5_vec_nonsplat_poison1(<3 x i32> %x, <3 x i16> %y) {93; CHECK-LABEL: @t5_vec_nonsplat_poison1(94; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>95; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>96; CHECK-NEXT: ret <3 x i16> [[T5]]97;98 %t0 = sub <3 x i16> <i16 32, i16 poison, i16 32>, %y99 %t1 = zext <3 x i16> %t0 to <3 x i32>100 %t2 = shl <3 x i32> %x, %t1101 %t3 = trunc <3 x i32> %t2 to <3 x i16>102 %t4 = add <3 x i16> %y, <i16 -24, i16 poison, i16 -24>103 %t5 = shl <3 x i16> %t3, %t4104 ret <3 x i16> %t5105}106 107; One-use tests108 109declare void @use16(i16)110declare void @use32(i32)111 112define i16 @t6_extrause0(i32 %x, i16 %y) {113; CHECK-LABEL: @t6_extrause0(114; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]115; CHECK-NEXT: [[T1:%.*]] = zext nneg i16 [[T0]] to i32116; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]117; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16118; CHECK-NEXT: call void @use16(i16 [[T3]])119; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X]] to i16120; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8121; CHECK-NEXT: ret i16 [[T5]]122;123 %t0 = sub i16 32, %y124 %t1 = zext i16 %t0 to i32125 %t2 = shl i32 %x, %t1126 %t3 = trunc i32 %t2 to i16127 %t4 = add i16 %y, -24128 call void @use16(i16 %t3)129 %t5 = shl i16 %t3, %t4130 ret i16 %t5131}132 133define i16 @t7_extrause1(i32 %x, i16 %y) {134; CHECK-LABEL: @t7_extrause1(135; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -24136; CHECK-NEXT: call void @use16(i16 [[T4]])137; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16138; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8139; CHECK-NEXT: ret i16 [[T5]]140;141 %t0 = sub i16 32, %y142 %t1 = zext i16 %t0 to i32143 %t2 = shl i32 %x, %t1144 %t3 = trunc i32 %t2 to i16145 %t4 = add i16 %y, -24146 call void @use16(i16 %t4)147 %t5 = shl i16 %t3, %t4148 ret i16 %t5149}150 151define i16 @t8_extrause2(i32 %x, i16 %y) {152; CHECK-LABEL: @t8_extrause2(153; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]154; CHECK-NEXT: [[T1:%.*]] = zext nneg i16 [[T0]] to i32155; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]156; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16157; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24158; CHECK-NEXT: call void @use16(i16 [[T3]])159; CHECK-NEXT: call void @use16(i16 [[T4]])160; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]161; CHECK-NEXT: ret i16 [[T5]]162;163 %t0 = sub i16 32, %y164 %t1 = zext i16 %t0 to i32165 %t2 = shl i32 %x, %t1166 %t3 = trunc i32 %t2 to i16167 %t4 = add i16 %y, -24168 call void @use16(i16 %t3)169 call void @use16(i16 %t4)170 %t5 = shl i16 %t3, %t4171 ret i16 %t5172}173 174; No 'nuw'/'nsw' flags are to be propagated!175; But we can't test that, such IR does not reach that code.176 177; Negative tests178 179; Can't fold, total shift would be 32180define i16 @n11(i32 %x, i16 %y) {181; CHECK-LABEL: @n11(182; CHECK-NEXT: [[T0:%.*]] = sub i16 30, [[Y:%.*]]183; CHECK-NEXT: [[T1:%.*]] = zext nneg i16 [[T0]] to i32184; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]185; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16186; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -31187; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]188; CHECK-NEXT: ret i16 [[T5]]189;190 %t0 = sub i16 30, %y191 %t1 = zext i16 %t0 to i32192 %t2 = shl i32 %x, %t1193 %t3 = trunc i32 %t2 to i16194 %t4 = add i16 %y, -31195 %t5 = shl i16 %t3, %t4196 ret i16 %t5197}198 199; Bit width mismatch of shift amount200 201@Y32 = global i32 42202@Y16 = global i16 42203define i16 @t01(i32 %x) {204; CHECK-LABEL: @t01(205; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], ptrtoint (ptr @Y32 to i32)206; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[T0]] to i16207; CHECK-NEXT: [[T2:%.*]] = shl i16 [[T1]], ptrtoint (ptr @Y16 to i16)208; CHECK-NEXT: ret i16 [[T2]]209;210 %t0 = shl i32 %x, ptrtoint (ptr @Y32 to i32)211 %t1 = trunc i32 %t0 to i16212 %t2 = shl i16 %t1, ptrtoint (ptr @Y16 to i16)213 ret i16 %t2214}215 216define i16 @shl_tr_shl_constant_shift_amount_uses(i32 %x) {217; CHECK-LABEL: @shl_tr_shl_constant_shift_amount_uses(218; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 3219; CHECK-NEXT: call void @use32(i32 [[SHL]])220; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SHL]] to i16221; CHECK-NEXT: call void @use16(i16 [[TR]])222; CHECK-NEXT: [[R:%.*]] = shl i16 [[TR]], 4223; CHECK-NEXT: ret i16 [[R]]224;225 %shl = shl i32 %x, 3226 call void @use32(i32 %shl)227 %tr = trunc i32 %shl to i16228 call void @use16(i16 %tr)229 %r = shl i16 %tr, 4230 ret i16 %r231}232 233; This would infinite loop because we did not process the234; poison shift before trying to fold shift-of-shift. To reach235; the problematic transform, it needs a datalayout to specify236; that the narrow types are legal, but i64 is not.237 238define i1 @PR51657(i64 %x, i1 %c1) {239; CHECK-LABEL: @PR51657(240; CHECK-NEXT: entry:241; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]242; CHECK: cond.false:243; CHECK-NEXT: br label [[COND_END]]244; CHECK: cond.end:245; CHECK-NEXT: ret i1 true246;247entry:248 br i1 %c1, label %cond.false, label %cond.end249 250cond.false:251 %shl = shl i64 %x, 64252 %conv26 = trunc i64 %shl to i32253 %t1 = trunc i64 %shl to i8254 br label %cond.end255 256cond.end:257 %cond = phi i32 [ %conv26, %cond.false ], [ 0, %entry ]258 %t2 = phi i8 [ %t1, %cond.false ], [ 0, %entry ]259 %conv27 = sext i8 %t2 to i32260 %eq = icmp eq i32 %cond, %conv27261 ret i1 %eq262}263 264 265define i16 @extra_use_on_first_shift(i32 %x) {266; CHECK-LABEL: @extra_use_on_first_shift(267; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 3268; CHECK-NEXT: call void @use32(i32 [[A]])269; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[A]] to i16270; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[TR]], 6271; CHECK-NEXT: ret i16 [[SH]]272;273 %a = ashr i32 %x, 3274 call void @use32(i32 %a)275 %tr = trunc i32 %a to i16276 %sh = lshr i16 %tr, 6277 ret i16 %sh278}279