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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine -S < %s | FileCheck %s3 4 5; If we only want bits that already match the signbit then we don't need to shift.6; https://alive2.llvm.org/ce/z/WJBPVt7define i32 @src_srem_shl_demand_max_signbit(i32 %a0) {8; CHECK-LABEL: @src_srem_shl_demand_max_signbit(9; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 210; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -214748364811; CHECK-NEXT: ret i32 [[MASK]]12;13 %srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD14 %shl = shl i32 %srem, 30 ; shl = SD00000000000000000000000000000015 %mask = and i32 %shl, -2147483648 ; mask = 1000000000000000000000000000000016 ret i32 %mask17}18 19define i32 @src_srem_shl_demand_min_signbit(i32 %a0) {20; CHECK-LABEL: @src_srem_shl_demand_min_signbit(21; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 107374182322; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -214748364823; CHECK-NEXT: ret i32 [[MASK]]24;25 %srem = srem i32 %a0, 1073741823 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD26 %shl = shl i32 %srem, 1 ; shl = SDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD027 %mask = and i32 %shl, -2147483648 ; mask = 1000000000000000000000000000000028 ret i32 %mask29}30 31define i32 @src_srem_shl_demand_max_mask(i32 %a0) {32; CHECK-LABEL: @src_srem_shl_demand_max_mask(33; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 234; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -435; CHECK-NEXT: ret i32 [[MASK]]36;37 %srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD38 %shl = shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD039 %mask = and i32 %shl, -4 ; mask = 1111111111111111111111111111110040 ret i32 %mask41}42 43; Negative test - mask demands non-signbit from shift source44define i32 @src_srem_shl_demand_max_signbit_mask_hit_first_demand(i32 %a0) {45; CHECK-LABEL: @src_srem_shl_demand_max_signbit_mask_hit_first_demand(46; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 447; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 2948; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -107374182449; CHECK-NEXT: ret i32 [[MASK]]50;51 %srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD52 %shl = shl i32 %srem, 29 ; shl = SDD0000000000000000000000000000053 %mask = and i32 %shl, -1073741824 ; mask = 1100000000000000000000000000000054 ret i32 %mask55}56 57define i32 @src_srem_shl_demand_min_signbit_mask_hit_last_demand(i32 %a0) {58; CHECK-LABEL: @src_srem_shl_demand_min_signbit_mask_hit_last_demand(59; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 53687091260; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 161; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -107374182262; CHECK-NEXT: ret i32 [[MASK]]63;64 %srem = srem i32 %a0, 536870912 ; srem = SSSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD65 %shl = shl i32 %srem, 1 ; shl = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD066 %mask = and i32 %shl, -1073741822 ; mask = 1100000000000000000000000000001067 ret i32 %mask68}69 70define i32 @src_srem_shl_demand_eliminate_signbit(i32 %a0) {71; CHECK-LABEL: @src_srem_shl_demand_eliminate_signbit(72; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 107374182473; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 174; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], 275; CHECK-NEXT: ret i32 [[MASK]]76;77 %srem = srem i32 %a0, 1073741824 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD78 %shl = shl i32 %srem, 1 ; shl = DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD079 %mask = and i32 %shl, 2 ; mask = 0000000000000000000000000000001080 ret i32 %mask81}82 83define i32 @src_srem_shl_demand_max_mask_hit_demand(i32 %a0) {84; CHECK-LABEL: @src_srem_shl_demand_max_mask_hit_demand(85; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 486; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 187; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -488; CHECK-NEXT: ret i32 [[MASK]]89;90 %srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD91 %shl= shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD092 %mask = and i32 %shl, -4 ; mask = 1111111111111111111111111111110093 ret i32 %mask94}95 96define <2 x i32> @src_srem_shl_mask_vector(<2 x i32> %a0) {97; CHECK-LABEL: @src_srem_shl_mask_vector(98; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 4)99; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> [[SREM]], splat (i32 29)100; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], splat (i32 -1073741824)101; CHECK-NEXT: ret <2 x i32> [[MASK]]102;103 %srem = srem <2 x i32> %a0, <i32 4, i32 4>104 %shl = shl <2 x i32> %srem, <i32 29, i32 29>105 %mask = and <2 x i32> %shl, <i32 -1073741824, i32 -1073741824>106 ret <2 x i32> %mask107}108 109define <2 x i32> @src_srem_shl_mask_vector_nonconstant(<2 x i32> %a0, <2 x i32> %a1) {110; CHECK-LABEL: @src_srem_shl_mask_vector_nonconstant(111; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 4)112; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[SREM]], [[A1:%.*]]113; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], splat (i32 -1073741824)114; CHECK-NEXT: ret <2 x i32> [[MASK]]115;116 %srem = srem <2 x i32> %a0, <i32 4, i32 4>117 %shl = shl <2 x i32> %srem, %a1118 %mask = and <2 x i32> %shl, <i32 -1073741824, i32 -1073741824>119 ret <2 x i32> %mask120}121 122define i16 @sext_shl_trunc_same_size(i16 %x, i32 %y) {123; CHECK-LABEL: @sext_shl_trunc_same_size(124; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32125; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]126; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i16127; CHECK-NEXT: ret i16 [[T]]128;129 %conv = sext i16 %x to i32130 %shl = shl i32 %conv, %y131 %t = trunc i32 %shl to i16132 ret i16 %t133}134 135define i5 @sext_shl_trunc_smaller(i16 %x, i32 %y) {136; CHECK-LABEL: @sext_shl_trunc_smaller(137; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32138; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]139; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i5140; CHECK-NEXT: ret i5 [[T]]141;142 %conv = sext i16 %x to i32143 %shl = shl i32 %conv, %y144 %t = trunc i32 %shl to i5145 ret i5 %t146}147 148; negative test - demanding 1 high-bit too many to change the extend149 150define i17 @sext_shl_trunc_larger(i16 %x, i32 %y) {151; CHECK-LABEL: @sext_shl_trunc_larger(152; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[X:%.*]] to i32153; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[Y:%.*]]154; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i17155; CHECK-NEXT: ret i17 [[T]]156;157 %conv = sext i16 %x to i32158 %shl = shl i32 %conv, %y159 %t = trunc i32 %shl to i17160 ret i17 %t161}162 163define i32 @sext_shl_mask(i16 %x, i32 %y) {164; CHECK-LABEL: @sext_shl_mask(165; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32166; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]167; CHECK-NEXT: [[T:%.*]] = and i32 [[SHL]], 65535168; CHECK-NEXT: ret i32 [[T]]169;170 %conv = sext i16 %x to i32171 %shl = shl i32 %conv, %y172 %t = and i32 %shl, 65535173 ret i32 %t174}175 176; negative test - demanding a bit that could change with sext177 178define i32 @sext_shl_mask_higher(i16 %x, i32 %y) {179; CHECK-LABEL: @sext_shl_mask_higher(180; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[X:%.*]] to i32181; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[Y:%.*]]182; CHECK-NEXT: [[T:%.*]] = and i32 [[SHL]], 65536183; CHECK-NEXT: ret i32 [[T]]184;185 %conv = sext i16 %x to i32186 %shl = shl i32 %conv, %y187 %t = and i32 %shl, 65536188 ret i32 %t189}190 191; May need some, but not all of the bits set by the 'or'.192 193define i32 @set_shl_mask(i32 %x, i32 %y) {194; CHECK-LABEL: @set_shl_mask(195; CHECK-NEXT: [[Z:%.*]] = or i32 [[X:%.*]], 65537196; CHECK-NEXT: [[S:%.*]] = shl i32 [[Z]], [[Y:%.*]]197; CHECK-NEXT: [[R:%.*]] = and i32 [[S]], 65536198; CHECK-NEXT: ret i32 [[R]]199;200 %z = or i32 %x, 196609201 %s = shl i32 %z, %y202 %r = and i32 %s, 65536203 ret i32 %r204}205 206; PR50341207 208define i8 @must_drop_poison(i32 %x, i32 %y) {209; CHECK-LABEL: @must_drop_poison(210; CHECK-NEXT: [[S:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]211; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S]] to i8212; CHECK-NEXT: ret i8 [[T]]213;214 %a = and i32 %x, 255215 %s = shl nuw nsw i32 %a, %y216 %t = trunc i32 %s to i8217 ret i8 %t218}219 220; This would infinite loop with D110170 / bb9333c3504a221 222define i32 @f_t15_t01_t09(i40 %t2) {223; CHECK-LABEL: @f_t15_t01_t09(224; CHECK-NEXT: [[SH_DIFF:%.*]] = ashr i40 [[T2:%.*]], 15225; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc nsw i40 [[SH_DIFF]] to i32226; CHECK-NEXT: [[SHL1:%.*]] = and i32 [[TR_SH_DIFF]], -65536227; CHECK-NEXT: ret i32 [[SHL1]]228;229 %downscale = ashr i40 %t2, 31230 %resize = trunc i40 %downscale to i32231 %shl1 = shl i32 %resize, 16232 %resize1 = ashr i32 %shl1, 16233 %r = shl i32 %resize1, 31234 ret i32 %shl1235}236