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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4target datalayout = "n8:16:32:64"5 6declare void @use(i32)7 8define i32 @sextinreg(i32 %x) {9; CHECK-LABEL: @sextinreg(10; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 1611; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 1612; CHECK-NEXT: ret i32 [[T3]]13;14 %t1 = and i32 %x, 6553515 %t2 = xor i32 %t1, -3276816 %t3 = add i32 %t2, 3276817 ret i32 %t318}19 20define i32 @sextinreg_extra_use(i32 %x) {21; CHECK-LABEL: @sextinreg_extra_use(22; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 6553523; CHECK-NEXT: [[T2:%.*]] = xor i32 [[T1]], -3276824; CHECK-NEXT: call void @use(i32 [[T2]])25; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], 3276826; CHECK-NEXT: ret i32 [[T3]]27;28 %t1 = and i32 %x, 6553529 %t2 = xor i32 %t1, -3276830 call void @use(i32 %t2)31 %t3 = add i32 %t2, 3276832 ret i32 %t333}34 35define <2 x i32> @sextinreg_splat(<2 x i32> %x) {36; CHECK-LABEL: @sextinreg_splat(37; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], splat (i32 16)38; CHECK-NEXT: [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], splat (i32 16)39; CHECK-NEXT: ret <2 x i32> [[T3]]40;41 %t1 = and <2 x i32> %x, <i32 65535, i32 65535>42 %t2 = xor <2 x i32> %t1, <i32 -32768, i32 -32768>43 %t3 = add <2 x i32> %t2, <i32 32768, i32 32768>44 ret <2 x i32> %t345}46 47define i32 @sextinreg_alt(i32 %x) {48; CHECK-LABEL: @sextinreg_alt(49; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 1650; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 1651; CHECK-NEXT: ret i32 [[T3]]52;53 %t1 = and i32 %x, 6553554 %t2 = xor i32 %t1, 3276855 %t3 = add i32 %t2, -3276856 ret i32 %t357}58 59define <2 x i32> @sextinreg_alt_splat(<2 x i32> %x) {60; CHECK-LABEL: @sextinreg_alt_splat(61; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], splat (i32 16)62; CHECK-NEXT: [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], splat (i32 16)63; CHECK-NEXT: ret <2 x i32> [[T3]]64;65 %t1 = and <2 x i32> %x, <i32 65535, i32 65535>66 %t2 = xor <2 x i32> %t1, <i32 32768, i32 32768>67 %t3 = add <2 x i32> %t2, <i32 -32768, i32 -32768>68 ret <2 x i32> %t369}70 71define i32 @sext(i16 %P) {72; CHECK-LABEL: @sext(73; CHECK-NEXT: [[T5:%.*]] = sext i16 [[P:%.*]] to i3274; CHECK-NEXT: ret i32 [[T5]]75;76 %t1 = zext i16 %P to i3277 %t4 = xor i32 %t1, 3276878 %t5 = add i32 %t4, -3276879 ret i32 %t580}81 82define i32 @sext_extra_use(i16 %P) {83; CHECK-LABEL: @sext_extra_use(84; CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[P:%.*]], -3276885; CHECK-NEXT: [[T4:%.*]] = zext i16 [[TMP1]] to i3286; CHECK-NEXT: call void @use(i32 [[T4]])87; CHECK-NEXT: [[T5:%.*]] = sext i16 [[P]] to i3288; CHECK-NEXT: ret i32 [[T5]]89;90 %t1 = zext i16 %P to i3291 %t4 = xor i32 %t1, 3276892 call void @use(i32 %t4)93 %t5 = add i32 %t4, -3276894 ret i32 %t595}96 97define <2 x i32> @sext_splat(<2 x i16> %P) {98; CHECK-LABEL: @sext_splat(99; CHECK-NEXT: [[T5:%.*]] = sext <2 x i16> [[P:%.*]] to <2 x i32>100; CHECK-NEXT: ret <2 x i32> [[T5]]101;102 %t1 = zext <2 x i16> %P to <2 x i32>103 %t4 = xor <2 x i32> %t1, <i32 32768, i32 32768>104 %t5 = add <2 x i32> %t4, <i32 -32768, i32 -32768>105 ret <2 x i32> %t5106}107 108define i32 @sextinreg2(i32 %x) {109; CHECK-LABEL: @sextinreg2(110; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 24111; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 24112; CHECK-NEXT: ret i32 [[T3]]113;114 %t1 = and i32 %x, 255115 %t2 = xor i32 %t1, 128116 %t3 = add i32 %t2, -128117 ret i32 %t3118}119 120define <2 x i32> @sextinreg2_splat(<2 x i32> %x) {121; CHECK-LABEL: @sextinreg2_splat(122; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], splat (i32 24)123; CHECK-NEXT: [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], splat (i32 24)124; CHECK-NEXT: ret <2 x i32> [[T3]]125;126 %t1 = and <2 x i32> %x, <i32 255, i32 255>127 %t2 = xor <2 x i32> %t1, <i32 128, i32 128>128 %t3 = add <2 x i32> %t2, <i32 -128, i32 -128>129 ret <2 x i32> %t3130}131 132define i32 @test5(i32 %x) {133; CHECK-LABEL: @test5(134; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], 16135; CHECK-NEXT: [[T4:%.*]] = ashr exact i32 [[T2]], 16136; CHECK-NEXT: ret i32 [[T4]]137;138 %t2 = shl i32 %x, 16139 %t4 = ashr i32 %t2, 16140 ret i32 %t4141}142 143; If the shift amount equals the difference in width of the destination144; and source scalar types:145; ashr (shl (zext X), C), C --> sext X146 147define i32 @test6(i16 %P) {148; CHECK-LABEL: @test6(149; CHECK-NEXT: [[T5:%.*]] = sext i16 [[P:%.*]] to i32150; CHECK-NEXT: ret i32 [[T5]]151;152 %t1 = zext i16 %P to i32153 %sext1 = shl i32 %t1, 16154 %t5 = ashr i32 %sext1, 16155 ret i32 %t5156}157 158; Vectors should get the same fold as above.159 160define <2 x i32> @test6_splat_vec(<2 x i12> %P) {161; CHECK-LABEL: @test6_splat_vec(162; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> [[P:%.*]] to <2 x i32>163; CHECK-NEXT: ret <2 x i32> [[ASHR]]164;165 %z = zext <2 x i12> %P to <2 x i32>166 %shl = shl <2 x i32> %z, <i32 20, i32 20>167 %ashr = ashr <2 x i32> %shl, <i32 20, i32 20>168 ret <2 x i32> %ashr169}170 171define i32 @ashr(i32 %x) {172; CHECK-LABEL: @ashr(173; CHECK-NEXT: [[SUB:%.*]] = ashr i32 [[X:%.*]], 5174; CHECK-NEXT: ret i32 [[SUB]]175;176 %shr = lshr i32 %x, 5177 %xor = xor i32 %shr, 67108864178 %sub = add i32 %xor, -67108864179 ret i32 %sub180}181 182define <2 x i32> @ashr_splat(<2 x i32> %x) {183; CHECK-LABEL: @ashr_splat(184; CHECK-NEXT: [[SUB:%.*]] = ashr <2 x i32> [[X:%.*]], splat (i32 5)185; CHECK-NEXT: ret <2 x i32> [[SUB]]186;187 %shr = lshr <2 x i32> %x, <i32 5, i32 5>188 %xor = xor <2 x i32> %shr, <i32 67108864, i32 67108864>189 %sub = add <2 x i32> %xor, <i32 -67108864, i32 -67108864>190 ret <2 x i32> %sub191}192