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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine %s -S -o - | FileCheck %s3 4; Clamp positive to allOnes:5; E.g., clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap.6; int32 clamp255(int32 v) {7; return (((255 - (v)) >> 31) | (v)) & 255;8; }9;10 11; Scalar Types12 13define i32 @clamp255_i32(i32 %x) {14; CHECK-LABEL: @clamp255_i32(15; CHECK-NEXT: [[OR:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)16; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR]], 25517; CHECK-NEXT: ret i32 [[AND]]18;19 %sub = sub nsw i32 255, %x20 %shr = ashr i32 %sub, 3121 %or = or i32 %shr, %x22 %and = and i32 %or, 25523 ret i32 %and24}25 26define i8 @sub_ashr_or_i8(i8 %x, i8 %y) {27; CHECK-LABEL: @sub_ashr_or_i8(28; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], [[X:%.*]]29; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i8 -1, i8 [[X]]30; CHECK-NEXT: ret i8 [[OR]]31;32 %sub = sub nsw i8 %y, %x33 %shr = ashr i8 %sub, 734 %or = or i8 %shr, %x35 ret i8 %or36}37 38define i16 @sub_ashr_or_i16(i16 %x, i16 %y) {39; CHECK-LABEL: @sub_ashr_or_i16(40; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i16 [[Y:%.*]], [[X:%.*]]41; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i16 -1, i16 [[X]]42; CHECK-NEXT: ret i16 [[OR]]43;44 %sub = sub nsw i16 %y, %x45 %shr = ashr i16 %sub, 1546 %or = or i16 %shr, %x47 ret i16 %or48}49 50define i32 @sub_ashr_or_i32(i32 %x, i32 %y) {51; CHECK-LABEL: @sub_ashr_or_i32(52; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]53; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]54; CHECK-NEXT: ret i32 [[OR]]55;56 %sub = sub nsw i32 %y, %x57 %shr = ashr i32 %sub, 3158 %or = or i32 %shr, %x59 ret i32 %or60}61 62define i64 @sub_ashr_or_i64(i64 %x, i64 %y) {63; CHECK-LABEL: @sub_ashr_or_i64(64; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[Y:%.*]], [[X:%.*]]65; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i64 -1, i64 [[X]]66; CHECK-NEXT: ret i64 [[OR]]67;68 %sub = sub nsw i64 %y, %x69 %shr = ashr i64 %sub, 6370 %or = or i64 %shr, %x71 ret i64 %or72}73 74define i32 @neg_or_ashr_i32(i32 %x) {75; CHECK-LABEL: @neg_or_ashr_i32(76; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 077; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i3278; CHECK-NEXT: ret i32 [[SHR]]79;80 %neg = sub i32 0, %x81 %or = or i32 %neg, %x82 %shr = ashr i32 %or, 3183 ret i32 %shr84}85 86; nuw nsw87 88define i32 @sub_ashr_or_i32_nuw_nsw(i32 %x, i32 %y) {89; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw(90; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]91; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]92; CHECK-NEXT: ret i32 [[OR]]93;94 %sub = sub nuw nsw i32 %y, %x95 %shr = ashr i32 %sub, 3196 %or = or i32 %shr, %x97 ret i32 %or98}99 100; Commute101 102define i32 @sub_ashr_or_i32_commute(i32 %x, i32 %y) {103; CHECK-LABEL: @sub_ashr_or_i32_commute(104; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]105; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]106; CHECK-NEXT: ret i32 [[OR]]107;108 %sub = sub nsw i32 %y, %x109 %shr = ashr i32 %sub, 31110 %or = or i32 %x, %shr ; commute %shr and %x111 ret i32 %or112}113 114define i32 @neg_or_ashr_i32_commute(i32 %x0) {115; CHECK-LABEL: @neg_or_ashr_i32_commute(116; CHECK-NEXT: [[X:%.*]] = sdiv i32 42, [[X0:%.*]]117; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], 0118; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i32119; CHECK-NEXT: ret i32 [[SHR]]120;121 %x = sdiv i32 42, %x0 ; thwart complexity-based canonicalization122 %neg = sub i32 0, %x123 %or = or i32 %x, %neg124 %shr = ashr i32 %or, 31125 ret i32 %shr126}127 128; Vector Types129 130define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %x, <4 x i32> %y) {131; CHECK-LABEL: @sub_ashr_or_i32_vec(132; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]133; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> [[X]]134; CHECK-NEXT: ret <4 x i32> [[OR]]135;136 %sub = sub nsw <4 x i32> %y, %x137 %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>138 %or = or <4 x i32> %shr, %x139 ret <4 x i32> %or140}141 142define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {143; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw(144; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]145; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> [[X]]146; CHECK-NEXT: ret <4 x i32> [[OR]]147;148 %sub = sub nuw nsw <4 x i32> %y, %x149 %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>150 %or = or <4 x i32> %shr, %x151 ret <4 x i32> %or152}153 154define <4 x i32> @neg_or_ashr_i32_vec(<4 x i32> %x) {155; CHECK-LABEL: @neg_or_ashr_i32_vec(156; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[X:%.*]], zeroinitializer157; CHECK-NEXT: [[SHR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>158; CHECK-NEXT: ret <4 x i32> [[SHR]]159;160 %neg = sub <4 x i32> zeroinitializer, %x161 %or = or <4 x i32> %neg, %x162 %shr = ashr <4 x i32> %or, <i32 31, i32 31, i32 31, i32 31>163 ret <4 x i32> %shr164}165 166define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {167; CHECK-LABEL: @sub_ashr_or_i32_vec_commute(168; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]169; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> [[X]]170; CHECK-NEXT: ret <4 x i32> [[OR]]171;172 %sub = sub nsw <4 x i32> %y, %x173 %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>174 %or = or <4 x i32> %x, %shr175 ret <4 x i32> %or176}177 178define <4 x i32> @neg_or_ashr_i32_vec_commute(<4 x i32> %x0) {179; CHECK-LABEL: @neg_or_ashr_i32_vec_commute(180; CHECK-NEXT: [[X:%.*]] = sdiv <4 x i32> splat (i32 42), [[X0:%.*]]181; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[X]], zeroinitializer182; CHECK-NEXT: [[SHR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>183; CHECK-NEXT: ret <4 x i32> [[SHR]]184;185 %x = sdiv <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %x0 ; thwart complexity-based canonicalization186 %neg = sub <4 x i32> zeroinitializer, %x187 %or = or <4 x i32> %x, %neg188 %shr = ashr <4 x i32> %or, <i32 31, i32 31, i32 31, i32 31>189 ret <4 x i32> %shr190}191 192; Extra uses193 194define i32 @sub_ashr_or_i32_extra_use_sub(i32 %x, i32 %y, ptr %p) {195; CHECK-LABEL: @sub_ashr_or_i32_extra_use_sub(196; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]197; CHECK-NEXT: store i32 [[SUB]], ptr [[P:%.*]], align 4198; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X]], [[Y]]199; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]200; CHECK-NEXT: ret i32 [[OR]]201;202 %sub = sub nsw i32 %y, %x203 store i32 %sub, ptr %p204 %shr = ashr i32 %sub, 31205 %or = or i32 %shr, %x206 ret i32 %or207}208 209define i32 @sub_ashr_or_i32_extra_use_or(i32 %x, i32 %y, ptr %p) {210; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or(211; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]212; CHECK-NEXT: [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]213; CHECK-NEXT: store i32 [[OR]], ptr [[P:%.*]], align 4214; CHECK-NEXT: ret i32 [[OR]]215;216 %sub = sub nsw i32 %y, %x217 %shr = ashr i32 %sub, 31218 %or = or i32 %shr, %x219 store i32 %or, ptr %p220 ret i32 %or221}222 223define i32 @neg_extra_use_or_ashr_i32(i32 %x, ptr %p) {224; CHECK-LABEL: @neg_extra_use_or_ashr_i32(225; CHECK-NEXT: [[NEG:%.*]] = sub i32 0, [[X:%.*]]226; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], 0227; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i32228; CHECK-NEXT: store i32 [[NEG]], ptr [[P:%.*]], align 4229; CHECK-NEXT: ret i32 [[SHR]]230;231 %neg = sub i32 0, %x232 %or = or i32 %neg, %x233 %shr = ashr i32 %or, 31234 store i32 %neg, ptr %p235 ret i32 %shr236}237 238; Negative Tests239 240define i32 @sub_ashr_or_i32_extra_use_ashr(i32 %x, i32 %y, ptr %p) {241; CHECK-LABEL: @sub_ashr_or_i32_extra_use_ashr(242; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]243; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i32244; CHECK-NEXT: store i32 [[SHR]], ptr [[P:%.*]], align 4245; CHECK-NEXT: [[OR:%.*]] = or i32 [[X]], [[SHR]]246; CHECK-NEXT: ret i32 [[OR]]247;248 %sub = sub nsw i32 %y, %x249 %shr = ashr i32 %sub, 31250 store i32 %shr, ptr %p251 %or = or i32 %shr, %x252 ret i32 %or253}254 255define i32 @sub_ashr_or_i32_no_nsw_nuw(i32 %x, i32 %y) {256; CHECK-LABEL: @sub_ashr_or_i32_no_nsw_nuw(257; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]258; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31259; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]260; CHECK-NEXT: ret i32 [[OR]]261;262 %sub = sub i32 %y, %x263 %shr = ashr i32 %sub, 31264 %or = or i32 %shr, %x265 ret i32 %or266}267 268define i32 @neg_or_extra_use_ashr_i32(i32 %x, ptr %p) {269; CHECK-LABEL: @neg_or_extra_use_ashr_i32(270; CHECK-NEXT: [[NEG:%.*]] = sub i32 0, [[X:%.*]]271; CHECK-NEXT: [[OR:%.*]] = or i32 [[X]], [[NEG]]272; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[OR]], 31273; CHECK-NEXT: store i32 [[OR]], ptr [[P:%.*]], align 4274; CHECK-NEXT: ret i32 [[SHR]]275;276 %neg = sub i32 0, %x277 %or = or i32 %neg, %x278 %shr = ashr i32 %or, 31279 store i32 %or, ptr %p280 ret i32 %shr281}282 283define <4 x i32> @sub_ashr_or_i32_vec_undef1(<4 x i32> %x) {284; CHECK-LABEL: @sub_ashr_or_i32_vec_undef1(285; CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, [[X:%.*]]286; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], splat (i32 31)287; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]288; CHECK-NEXT: ret <4 x i32> [[OR]]289;290 %sub = sub <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, %x291 %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>292 %or = or <4 x i32> %shr, %x293 ret <4 x i32> %or294}295 296define <4 x i32> @sub_ashr_or_i32_vec_undef2(<4 x i32> %x) {297; CHECK-LABEL: @sub_ashr_or_i32_vec_undef2(298; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> splat (i32 255), [[X:%.*]]299; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 undef, i32 31, i32 31, i32 31>300; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]301; CHECK-NEXT: ret <4 x i32> [[OR]]302;303 %sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %x304 %shr = ashr <4 x i32> %sub, <i32 undef, i32 31, i32 31, i32 31>305 %or = or <4 x i32> %shr, %x306 ret <4 x i32> %or307}308 309define i32 @sub_ashr_or_i32_shift_wrong_bit(i32 %x, i32 %y) {310; CHECK-LABEL: @sub_ashr_or_i32_shift_wrong_bit(311; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]312; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 11313; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]314; CHECK-NEXT: ret i32 [[OR]]315;316 %sub = sub nsw i32 %y, %x317 %shr = ashr i32 %sub, 11318 %or = or i32 %shr, %x319 ret i32 %or320}321