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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4target datalayout = "n8:32"5 6; PR45487define i8 @udiv_i8(i8 %a, i8 %b) {8; CHECK-LABEL: @udiv_i8(9; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 [[A:%.*]], [[B:%.*]]10; CHECK-NEXT: ret i8 [[TMP1]]11;12 %za = zext i8 %a to i3213 %zb = zext i8 %b to i3214 %udiv = udiv i32 %za, %zb15 %conv3 = trunc i32 %udiv to i816 ret i8 %conv317}18 19define <2 x i8> @udiv_i8_vec(<2 x i8> %a, <2 x i8> %b) {20; CHECK-LABEL: @udiv_i8_vec(21; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i8> [[A:%.*]], [[B:%.*]]22; CHECK-NEXT: ret <2 x i8> [[TMP1]]23;24 %za = zext <2 x i8> %a to <2 x i32>25 %zb = zext <2 x i8> %b to <2 x i32>26 %udiv = udiv <2 x i32> %za, %zb27 %conv3 = trunc <2 x i32> %udiv to <2 x i8>28 ret <2 x i8> %conv329}30 31define i8 @urem_i8(i8 %a, i8 %b) {32; CHECK-LABEL: @urem_i8(33; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[A:%.*]], [[B:%.*]]34; CHECK-NEXT: ret i8 [[TMP1]]35;36 %za = zext i8 %a to i3237 %zb = zext i8 %b to i3238 %udiv = urem i32 %za, %zb39 %conv3 = trunc i32 %udiv to i840 ret i8 %conv341}42 43define <2 x i8> @urem_i8_vec(<2 x i8> %a, <2 x i8> %b) {44; CHECK-LABEL: @urem_i8_vec(45; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> [[A:%.*]], [[B:%.*]]46; CHECK-NEXT: ret <2 x i8> [[TMP1]]47;48 %za = zext <2 x i8> %a to <2 x i32>49 %zb = zext <2 x i8> %b to <2 x i32>50 %udiv = urem <2 x i32> %za, %zb51 %conv3 = trunc <2 x i32> %udiv to <2 x i8>52 ret <2 x i8> %conv353}54 55define i32 @udiv_i32(i8 %a, i8 %b) {56; CHECK-LABEL: @udiv_i32(57; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 [[A:%.*]], [[B:%.*]]58; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[TMP1]] to i3259; CHECK-NEXT: ret i32 [[UDIV]]60;61 %za = zext i8 %a to i3262 %zb = zext i8 %b to i3263 %udiv = udiv i32 %za, %zb64 ret i32 %udiv65}66 67define <2 x i32> @udiv_i32_vec(<2 x i8> %a, <2 x i8> %b) {68; CHECK-LABEL: @udiv_i32_vec(69; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i8> [[A:%.*]], [[B:%.*]]70; CHECK-NEXT: [[UDIV:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>71; CHECK-NEXT: ret <2 x i32> [[UDIV]]72;73 %za = zext <2 x i8> %a to <2 x i32>74 %zb = zext <2 x i8> %b to <2 x i32>75 %udiv = udiv <2 x i32> %za, %zb76 ret <2 x i32> %udiv77}78 79define i32 @udiv_i32_multiuse(i8 %a, i8 %b) {80; CHECK-LABEL: @udiv_i32_multiuse(81; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[A:%.*]] to i3282; CHECK-NEXT: [[ZB:%.*]] = zext i8 [[B:%.*]] to i3283; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ZA]], [[ZB]]84; CHECK-NEXT: [[EXTRA_USES:%.*]] = add nuw nsw i32 [[ZA]], [[ZB]]85; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[UDIV]], [[EXTRA_USES]]86; CHECK-NEXT: ret i32 [[R]]87;88 %za = zext i8 %a to i3289 %zb = zext i8 %b to i3290 %udiv = udiv i32 %za, %zb91 %extra_uses = add i32 %za, %zb92 %r = mul i32 %udiv, %extra_uses93 ret i32 %r94}95 96define i32 @udiv_illegal_type(i9 %a, i9 %b) {97; CHECK-LABEL: @udiv_illegal_type(98; CHECK-NEXT: [[TMP1:%.*]] = udiv i9 [[A:%.*]], [[B:%.*]]99; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[TMP1]] to i32100; CHECK-NEXT: ret i32 [[UDIV]]101;102 %za = zext i9 %a to i32103 %zb = zext i9 %b to i32104 %udiv = udiv i32 %za, %zb105 ret i32 %udiv106}107 108define i32 @urem_i32(i8 %a, i8 %b) {109; CHECK-LABEL: @urem_i32(110; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[A:%.*]], [[B:%.*]]111; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32112; CHECK-NEXT: ret i32 [[UREM]]113;114 %za = zext i8 %a to i32115 %zb = zext i8 %b to i32116 %urem = urem i32 %za, %zb117 ret i32 %urem118}119 120define <2 x i32> @urem_i32_vec(<2 x i8> %a, <2 x i8> %b) {121; CHECK-LABEL: @urem_i32_vec(122; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> [[A:%.*]], [[B:%.*]]123; CHECK-NEXT: [[UREM:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>124; CHECK-NEXT: ret <2 x i32> [[UREM]]125;126 %za = zext <2 x i8> %a to <2 x i32>127 %zb = zext <2 x i8> %b to <2 x i32>128 %urem = urem <2 x i32> %za, %zb129 ret <2 x i32> %urem130}131 132define i32 @urem_i32_multiuse(i8 %a, i8 %b) {133; CHECK-LABEL: @urem_i32_multiuse(134; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[A:%.*]] to i32135; CHECK-NEXT: [[ZB:%.*]] = zext i8 [[B:%.*]] to i32136; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], [[ZB]]137; CHECK-NEXT: [[EXTRA_USES:%.*]] = add nuw nsw i32 [[ZA]], [[ZB]]138; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[UREM]], [[EXTRA_USES]]139; CHECK-NEXT: ret i32 [[R]]140;141 %za = zext i8 %a to i32142 %zb = zext i8 %b to i32143 %urem = urem i32 %za, %zb144 %extra_uses = add i32 %za, %zb145 %r = mul i32 %urem, %extra_uses146 ret i32 %r147}148 149define i32 @urem_illegal_type(i9 %a, i9 %b) {150; CHECK-LABEL: @urem_illegal_type(151; CHECK-NEXT: [[TMP1:%.*]] = urem i9 [[A:%.*]], [[B:%.*]]152; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32153; CHECK-NEXT: ret i32 [[UREM]]154;155 %za = zext i9 %a to i32156 %zb = zext i9 %b to i32157 %urem = urem i32 %za, %zb158 ret i32 %urem159}160 161define i32 @udiv_i32_c(i8 %a) {162; CHECK-LABEL: @udiv_i32_c(163; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 [[A:%.*]], 10164; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i8 [[TMP1]] to i32165; CHECK-NEXT: ret i32 [[UDIV]]166;167 %za = zext i8 %a to i32168 %udiv = udiv i32 %za, 10169 ret i32 %udiv170}171 172define <2 x i32> @udiv_i32_c_vec(<2 x i8> %a) {173; CHECK-LABEL: @udiv_i32_c_vec(174; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i8> [[A:%.*]], <i8 10, i8 17>175; CHECK-NEXT: [[UDIV:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>176; CHECK-NEXT: ret <2 x i32> [[UDIV]]177;178 %za = zext <2 x i8> %a to <2 x i32>179 %udiv = udiv <2 x i32> %za, <i32 10, i32 17>180 ret <2 x i32> %udiv181}182 183define i32 @udiv_i32_c_multiuse(i8 %a) {184; CHECK-LABEL: @udiv_i32_c_multiuse(185; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[A:%.*]] to i32186; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ZA]], 10187; CHECK-NEXT: [[EXTRA_USE:%.*]] = add nuw nsw i32 [[UDIV]], [[ZA]]188; CHECK-NEXT: ret i32 [[EXTRA_USE]]189;190 %za = zext i8 %a to i32191 %udiv = udiv i32 %za, 10192 %extra_use = add i32 %za, %udiv193 ret i32 %extra_use194}195 196define i32 @udiv_illegal_type_c(i9 %a) {197; CHECK-LABEL: @udiv_illegal_type_c(198; CHECK-NEXT: [[TMP1:%.*]] = udiv i9 [[A:%.*]], 10199; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i9 [[TMP1]] to i32200; CHECK-NEXT: ret i32 [[UDIV]]201;202 %za = zext i9 %a to i32203 %udiv = udiv i32 %za, 10204 ret i32 %udiv205}206 207define i32 @urem_i32_c(i8 %a) {208; CHECK-LABEL: @urem_i32_c(209; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[A:%.*]], 10210; CHECK-NEXT: [[UREM:%.*]] = zext nneg i8 [[TMP1]] to i32211; CHECK-NEXT: ret i32 [[UREM]]212;213 %za = zext i8 %a to i32214 %urem = urem i32 %za, 10215 ret i32 %urem216}217 218define <2 x i32> @urem_i32_c_vec(<2 x i8> %a) {219; CHECK-LABEL: @urem_i32_c_vec(220; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> [[A:%.*]], <i8 10, i8 17>221; CHECK-NEXT: [[UREM:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32>222; CHECK-NEXT: ret <2 x i32> [[UREM]]223;224 %za = zext <2 x i8> %a to <2 x i32>225 %urem = urem <2 x i32> %za, <i32 10, i32 17>226 ret <2 x i32> %urem227}228 229define i32 @urem_i32_c_multiuse(i8 %a) {230; CHECK-LABEL: @urem_i32_c_multiuse(231; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[A:%.*]] to i32232; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], 10233; CHECK-NEXT: [[EXTRA_USE:%.*]] = add nuw nsw i32 [[UREM]], [[ZA]]234; CHECK-NEXT: ret i32 [[EXTRA_USE]]235;236 %za = zext i8 %a to i32237 %urem = urem i32 %za, 10238 %extra_use = add i32 %za, %urem239 ret i32 %extra_use240}241 242define i32 @urem_illegal_type_c(i9 %a) {243; CHECK-LABEL: @urem_illegal_type_c(244; CHECK-NEXT: [[TMP1:%.*]] = urem i9 [[A:%.*]], 10245; CHECK-NEXT: [[UREM:%.*]] = zext nneg i9 [[TMP1]] to i32246; CHECK-NEXT: ret i32 [[UREM]]247;248 %za = zext i9 %a to i32249 %urem = urem i32 %za, 10250 ret i32 %urem251}252 253define i32 @udiv_c_i32(i8 %a) {254; CHECK-LABEL: @udiv_c_i32(255; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 10, [[A:%.*]]256; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i8 [[TMP1]] to i32257; CHECK-NEXT: ret i32 [[UDIV]]258;259 %za = zext i8 %a to i32260 %udiv = udiv i32 10, %za261 ret i32 %udiv262}263 264define i32 @urem_c_i32(i8 %a) {265; CHECK-LABEL: @urem_c_i32(266; CHECK-NEXT: [[TMP1:%.*]] = urem i8 10, [[A:%.*]]267; CHECK-NEXT: [[UREM:%.*]] = zext nneg i8 [[TMP1]] to i32268; CHECK-NEXT: ret i32 [[UREM]]269;270 %za = zext i8 %a to i32271 %urem = urem i32 10, %za272 ret i32 %urem273}274 275; Make sure constexpr is handled.276 277@b = external global [1 x i8]278 279define i32 @udiv_constexpr(i8 %a) {280; CHECK-LABEL: @udiv_constexpr(281; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 [[A:%.*]], ptrtoint (ptr @b to i8)282; CHECK-NEXT: [[D:%.*]] = zext i8 [[TMP1]] to i32283; CHECK-NEXT: ret i32 [[D]]284;285 %za = zext i8 %a to i32286 %zb = zext i8 ptrtoint (ptr @b to i8) to i32287 %d = udiv i32 %za, %zb288 ret i32 %d289}290 291; minimal form of PR56810292 293@g1 = external global [1 x i8]294 295define i32 @udiv_const_constexpr(i8 %a) {296; CHECK-LABEL: @udiv_const_constexpr(297; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 42, ptrtoint (ptr @g1 to i8)298; CHECK-NEXT: [[D:%.*]] = zext nneg i8 [[TMP1]] to i32299; CHECK-NEXT: ret i32 [[D]]300;301 %z = zext i8 ptrtoint (ptr @g1 to i8) to i32302 %d = udiv i32 42, %z303 ret i32 %d304}305 306; minimal form of PR56810307 308@g2 = external global [1 x i8]309 310define i32 @urem_const_constexpr(i8 %a) {311; CHECK-LABEL: @urem_const_constexpr(312; CHECK-NEXT: [[TMP1:%.*]] = urem i8 42, ptrtoint (ptr @g2 to i8)313; CHECK-NEXT: [[D:%.*]] = zext nneg i8 [[TMP1]] to i32314; CHECK-NEXT: ret i32 [[D]]315;316 %z = zext i8 ptrtoint (ptr @g2 to i8) to i32317 %d = urem i32 42, %z318 ret i32 %d319}320 321@g3 = external global [1 x i8]322 323define i32 @udiv_constexpr_const(i8 %a) {324; CHECK-LABEL: @udiv_constexpr_const(325; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 ptrtoint (ptr @g3 to i8), 42326; CHECK-NEXT: [[D:%.*]] = zext nneg i8 [[TMP1]] to i32327; CHECK-NEXT: ret i32 [[D]]328;329 %z = zext i8 ptrtoint (ptr @g3 to i8) to i32330 %d = udiv i32 %z, 42331 ret i32 %d332}333 334@g4 = external global [1 x i8]335 336define i32 @urem_constexpr_const(i8 %a) {337; CHECK-LABEL: @urem_constexpr_const(338; CHECK-NEXT: [[TMP1:%.*]] = urem i8 ptrtoint (ptr @g4 to i8), 42339; CHECK-NEXT: [[D:%.*]] = zext nneg i8 [[TMP1]] to i32340; CHECK-NEXT: ret i32 [[D]]341;342 %z = zext i8 ptrtoint (ptr @g4 to i8) to i32343 %d = urem i32 %z, 42344 ret i32 %d345}346