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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define <8 x i16> @udiv_vec8x16(<8 x i16> %var) {5; CHECK-LABEL: define <8 x i16> @udiv_vec8x16(6; CHECK-SAME: <8 x i16> [[VAR:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: [[TMP0:%.*]] = lshr <8 x i16> [[VAR]], splat (i16 5)9; CHECK-NEXT: ret <8 x i16> [[TMP0]]10;11entry:12%0 = udiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>13ret <8 x i16> %014}15 16define <4 x i32> @udiv_vec4x32(<4 x i32> %var) {17; CHECK-LABEL: define <4 x i32> @udiv_vec4x32(18; CHECK-SAME: <4 x i32> [[VAR:%.*]]) {19; CHECK-NEXT: [[ENTRY:.*:]]20; CHECK-NEXT: [[TMP0:%.*]] = lshr <4 x i32> [[VAR]], splat (i32 4)21; CHECK-NEXT: ret <4 x i32> [[TMP0]]22;23entry:24%0 = udiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>25ret <4 x i32> %026}27