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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i1 @vec_reduce_umax_non_zero(<4 x i8> %xx) {5; CHECK-LABEL: @vec_reduce_umax_non_zero(6; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], <i8 0, i8 1, i8 0, i8 0>7; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])8; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 09; CHECK-NEXT: ret i1 [[R]]10;11 %x = add nuw <4 x i8> %xx, <i8 0, i8 1, i8 0, i8 0>12 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)13 %r = icmp eq i8 %v, 014 ret i1 %r15}16 17define i1 @vec_reduce_umax_non_zero_fail(<4 x i8> %xx) {18; CHECK-LABEL: @vec_reduce_umax_non_zero_fail(19; CHECK-NEXT: [[X:%.*]] = add nsw <4 x i8> [[XX:%.*]], splat (i8 1)20; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])21; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 022; CHECK-NEXT: ret i1 [[R]]23;24 %x = add nsw <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>25 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)26 %r = icmp eq i8 %v, 027 ret i1 %r28}29 30define i1 @vec_reduce_umin_non_zero(<4 x i8> %xx) {31; CHECK-LABEL: @vec_reduce_umin_non_zero(32; CHECK-NEXT: ret i1 false33;34 %x = add nuw <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>35 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)36 %r = icmp eq i8 %v, 037 ret i1 %r38}39 40define i1 @vec_reduce_umin_non_zero_fail(<4 x i8> %xx) {41; CHECK-LABEL: @vec_reduce_umin_non_zero_fail(42; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], <i8 0, i8 1, i8 1, i8 1>43; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]])44; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 045; CHECK-NEXT: ret i1 [[R]]46;47 %x = add nuw <4 x i8> %xx, <i8 0, i8 1, i8 1, i8 1>48 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)49 %r = icmp eq i8 %v, 050 ret i1 %r51}52 53define i1 @vec_reduce_smax_non_zero0(<4 x i8> %xx) {54; CHECK-LABEL: @vec_reduce_smax_non_zero0(55; CHECK-NEXT: ret i1 false56;57 %x = add nuw <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>58 %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x)59 %r = icmp eq i8 %v, 060 ret i1 %r61}62 63define i1 @vec_reduce_smax_non_zero1(<4 x i8> %xx) {64; CHECK-LABEL: @vec_reduce_smax_non_zero1(65; CHECK-NEXT: [[X0:%.*]] = and <4 x i8> [[XX:%.*]], <i8 127, i8 -1, i8 -1, i8 -1>66; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[X0]], <i8 1, i8 0, i8 0, i8 0>67; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]])68; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 069; CHECK-NEXT: ret i1 [[R]]70;71 %x0 = and <4 x i8> %xx, <i8 127, i8 255, i8 255, i8 255>72 %x = or <4 x i8> %x0, <i8 1, i8 0, i8 0, i8 0>73 %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x)74 %r = icmp eq i8 %v, 075 ret i1 %r76}77 78define i1 @vec_reduce_smax_non_zero_fail(<4 x i8> %xx) {79; CHECK-LABEL: @vec_reduce_smax_non_zero_fail(80; CHECK-NEXT: [[X0:%.*]] = and <4 x i8> [[XX:%.*]], <i8 127, i8 -1, i8 -1, i8 -1>81; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[X0]], <i8 1, i8 0, i8 0, i8 0>82; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]])83; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 084; CHECK-NEXT: ret i1 [[R]]85;86 %x0 = and <4 x i8> %xx, <i8 127, i8 255, i8 255, i8 255>87 %x = add nuw <4 x i8> %x0, <i8 1, i8 0, i8 0, i8 0>88 %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x)89 %r = icmp eq i8 %v, 090 ret i1 %r91}92 93define i1 @vec_reduce_smin_non_zero0(<4 x i8> %xx) {94; CHECK-LABEL: @vec_reduce_smin_non_zero0(95; CHECK-NEXT: ret i1 false96;97 %x = add nuw <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>98 %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x)99 %r = icmp eq i8 %v, 0100 ret i1 %r101}102 103define i1 @vec_reduce_smin_non_zero1(<4 x i8> %xx) {104; CHECK-LABEL: @vec_reduce_smin_non_zero1(105; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 0, i8 0, i8 0, i8 -128>106; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]])107; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0108; CHECK-NEXT: ret i1 [[R]]109;110 %x = or <4 x i8> %xx, <i8 0, i8 0, i8 0, i8 128>111 %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x)112 %r = icmp eq i8 %v, 0113 ret i1 %r114}115 116define i1 @vec_reduce_smin_non_zero_fail(<4 x i8> %xx) {117; CHECK-LABEL: @vec_reduce_smin_non_zero_fail(118; CHECK-NEXT: [[X0:%.*]] = or <4 x i8> [[XX:%.*]], <i8 0, i8 0, i8 0, i8 -128>119; CHECK-NEXT: [[X:%.*]] = add <4 x i8> [[X0]], <i8 0, i8 0, i8 0, i8 1>120; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]])121; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0122; CHECK-NEXT: ret i1 [[R]]123;124 %x0 = or <4 x i8> %xx, <i8 0, i8 0, i8 0, i8 128>125 %x = add <4 x i8> %x0, <i8 0, i8 0, i8 0, i8 1>126 %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x)127 %r = icmp eq i8 %v, 0128 ret i1 %r129}130 131define i8 @vec_reduce_umax_known0(<4 x i8> %xx) {132; CHECK-LABEL: @vec_reduce_umax_known0(133; CHECK-NEXT: ret i8 1134;135 %x = or <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>136 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)137 %r = and i8 %v, 1138 ret i8 %r139}140 141define i8 @vec_reduce_umax_known1(<4 x i8> %xx) {142; CHECK-LABEL: @vec_reduce_umax_known1(143; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 1, i8 1, i8 1, i8 -128>144; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])145; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], -128146; CHECK-NEXT: ret i8 [[R]]147;148 %x = or <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 128>149 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)150 %r = and i8 %v, 128151 ret i8 %r152}153 154define i8 @vec_reduce_umax_known_fail0(<4 x i8> %xx) {155; CHECK-LABEL: @vec_reduce_umax_known_fail0(156; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 1, i8 1, i8 1, i8 -128>157; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])158; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1159; CHECK-NEXT: ret i8 [[R]]160;161 %x = or <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 128>162 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)163 %r = and i8 %v, 1164 ret i8 %r165}166 167define i8 @vec_reduce_umax_known_fail1(<4 x i8> %xx) {168; CHECK-LABEL: @vec_reduce_umax_known_fail1(169; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 1, i8 2, i8 4, i8 8>170; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])171; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1172; CHECK-NEXT: ret i8 [[R]]173;174 %x = or <4 x i8> %xx, <i8 1, i8 2, i8 4, i8 8>175 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)176 %r = and i8 %v, 1177 ret i8 %r178}179 180define i8 @vec_reduce_umin_known0(<4 x i8> %xx) {181; CHECK-LABEL: @vec_reduce_umin_known0(182; CHECK-NEXT: ret i8 1183;184 %x = or <4 x i8> %xx, <i8 1, i8 1, i8 1, i8 1>185 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)186 %r = and i8 %v, 1187 ret i8 %r188}189 190define i8 @vec_reduce_umin_known1(<4 x i8> %xx) {191; CHECK-LABEL: @vec_reduce_umin_known1(192; CHECK-NEXT: [[X:%.*]] = and <4 x i8> [[XX:%.*]], <i8 127, i8 -1, i8 -1, i8 -1>193; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]])194; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], -128195; CHECK-NEXT: ret i8 [[R]]196;197 %x = and <4 x i8> %xx, <i8 127, i8 255, i8 255, i8 255>198 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)199 %r = and i8 %v, 128200 ret i8 %r201}202 203define i8 @vec_reduce_umin_known_fail0(<4 x i8> %xx) {204; CHECK-LABEL: @vec_reduce_umin_known_fail0(205; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 1, i8 0, i8 0, i8 0>206; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]])207; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1208; CHECK-NEXT: ret i8 [[R]]209;210 %x0 = and <4 x i8> %xx, <i8 127, i8 255, i8 255, i8 255>211 %x = or <4 x i8> %xx, <i8 1, i8 0, i8 0, i8 0>212 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)213 %r = and i8 %v, 1214 ret i8 %r215}216 217define i8 @vec_reduce_umin_known_fail1(<4 x i8> %xx) {218; CHECK-LABEL: @vec_reduce_umin_known_fail1(219; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 1, i8 2, i8 4, i8 8>220; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]])221; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1222; CHECK-NEXT: ret i8 [[R]]223;224 %x = or <4 x i8> %xx, <i8 1, i8 2, i8 4, i8 8>225 %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x)226 %r = and i8 %v, 1227 ret i8 %r228}229 230define i8 @vec_reduce_smax_known(<4 x i8> %xx) {231; CHECK-LABEL: @vec_reduce_smax_known(232; CHECK-NEXT: ret i8 4233;234 %x = or <4 x i8> %xx, <i8 4, i8 4, i8 4, i8 5>235 %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x)236 %r = and i8 %v, 4237 ret i8 %r238}239 240define i8 @vec_reduce_smax_known_fail(<4 x i8> %xx) {241; CHECK-LABEL: @vec_reduce_smax_known_fail(242; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 4, i8 4, i8 8, i8 5>243; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]])244; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 4245; CHECK-NEXT: ret i8 [[R]]246;247 %x = or <4 x i8> %xx, <i8 4, i8 4, i8 8, i8 5>248 %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x)249 %r = and i8 %v, 4250 ret i8 %r251}252 253define i8 @vec_reduce_smin_known(<4 x i8> %xx) {254; CHECK-LABEL: @vec_reduce_smin_known(255; CHECK-NEXT: ret i8 8256;257 %x = or <4 x i8> %xx, <i8 8, i8 24, i8 56, i8 9>258 %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x)259 %r = and i8 %v, 8260 ret i8 %r261}262 263define i8 @vec_reduce_smin_known_fail(<4 x i8> %xx) {264; CHECK-LABEL: @vec_reduce_smin_known_fail(265; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 8, i8 23, i8 56, i8 9>266; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]])267; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 8268; CHECK-NEXT: ret i8 [[R]]269;270 %x = or <4 x i8> %xx, <i8 8, i8 23, i8 56, i8 9>271 %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x)272 %r = and i8 %v, 8273 ret i8 %r274}275