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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes='instcombine' -S < %s | FileCheck %s3target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"4 5define i64 @promote_vscale_i32_to_i64() {6; CHECK-LABEL: @promote_vscale_i32_to_i64(7; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()8; CHECK-NEXT: [[EXT:%.*]] = and i64 [[VSCALE]], 42949672959; CHECK-NEXT: ret i64 [[EXT]]10;11 %vscale = call i32 @llvm.vscale.i32()12 %ext = zext i32 %vscale to i6413 ret i64 %ext14}15 16define i64 @pomote_zext_shl_vscale_i32_to_i64() {17; CHECK-LABEL: @pomote_zext_shl_vscale_i32_to_i64(18; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()19; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[VSCALE]], 320; CHECK-NEXT: [[EXT:%.*]] = and i64 [[SHL]], 429496728821; CHECK-NEXT: ret i64 [[EXT]]22;23 %vscale = call i32 @llvm.vscale.i32()24 %shl = shl i32 %vscale, 325 %ext = zext i32 %shl to i6426 ret i64 %ext27}28 29; Same test as @pomote_zext_shl_vscale_i32_to_i64, but with the30; vscale_range attribute so that the 'and' is folded away.31define i64 @free_zext_vscale_shl_i32_to_i64() #0 {32; CHECK-LABEL: @free_zext_vscale_shl_i32_to_i64(33; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()34; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[VSCALE]], 335; CHECK-NEXT: ret i64 [[SHL]]36;37 %vscale = call i32 @llvm.vscale.i32()38 %shl = shl i32 %vscale, 339 %ext = zext i32 %shl to i6440 ret i64 %ext41}42 43declare i32 @llvm.vscale.i32()44 45attributes #0 = { vscale_range(1,16) }46