289 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {5; CHECK-LABEL: @zext_or_icmp_icmp(6; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 17; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 08; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 09; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TOBOOL1]], [[TOBOOL2]]10; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i811; CHECK-NEXT: ret i8 [[ZEXT]]12;13 %mask = and i8 %a, 114 %toBool1 = icmp eq i8 %mask, 015 %toBool2 = icmp eq i8 %b, 016 %bothCond = or i1 %toBool1, %toBool217 %zext = zext i1 %bothCond to i818 ret i8 %zext19}20 21define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) {22; CHECK-LABEL: @zext_or_icmp_icmp_logical(23; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 124; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 025; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 026; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]]27; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i828; CHECK-NEXT: ret i8 [[ZEXT]]29;30 %mask = and i8 %a, 131 %toBool1 = icmp eq i8 %mask, 032 %toBool2 = icmp eq i8 %b, 033 %bothCond = select i1 %toBool1, i1 true, i1 %toBool234 %zext = zext i1 %bothCond to i835 ret i8 %zext36}37 38; Here, widening the or from i1 to i32 and removing one of the icmps would39; widen an undef value (created by the out-of-range shift), increasing the40; range of valid values for the return, so we can't do it.41 42define i32 @dont_widen_undef() {43; CHECK-LABEL: @dont_widen_undef(44; CHECK-NEXT: entry:45; CHECK-NEXT: br label [[BLOCK2:%.*]]46; CHECK: block1:47; CHECK-NEXT: br label [[BLOCK2]]48; CHECK: block2:49; CHECK-NEXT: ret i32 150;51entry:52 br label %block253 54block1:55 br label %block256 57block2:58 %m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]59 %cmp.i = icmp ugt i32 %m.011, 160 %m.1.op = lshr i32 1, %m.01161 %sext.mask = and i32 %m.1.op, 6553562 %cmp115 = icmp ne i32 %sext.mask, 063 %cmp1 = or i1 %cmp.i, %cmp11564 %conv2 = zext i1 %cmp1 to i3265 ret i32 %conv266}67 68define i32 @dont_widen_undef_logical() {69; CHECK-LABEL: @dont_widen_undef_logical(70; CHECK-NEXT: entry:71; CHECK-NEXT: br label [[BLOCK2:%.*]]72; CHECK: block1:73; CHECK-NEXT: br label [[BLOCK2]]74; CHECK: block2:75; CHECK-NEXT: ret i32 176;77entry:78 br label %block279 80block1:81 br label %block282 83block2:84 %m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]85 %cmp.i = icmp ugt i32 %m.011, 186 %m.1.op = lshr i32 1, %m.01187 %sext.mask = and i32 %m.1.op, 6553588 %cmp115 = icmp ne i32 %sext.mask, 089 %cmp1 = select i1 %cmp.i, i1 true, i1 %cmp11590 %conv2 = zext i1 %cmp1 to i3291 ret i32 %conv292}93 94; A limitation of knownbits with overshift prevents reducing to 'false'.95 96define i1 @knownbits_out_of_range_shift(i32 %x) {97; CHECK-LABEL: @knownbits_out_of_range_shift(98; CHECK-NEXT: entry:99; CHECK-NEXT: br label [[BLOCK2:%.*]]100; CHECK: block1:101; CHECK-NEXT: br label [[BLOCK2]]102; CHECK: block2:103; CHECK-NEXT: ret i1 false104;105entry:106 br label %block2107 108block1:109 br label %block2110 111block2:112 %p = phi i32 [ 63, %entry ], [ 31, %block1 ]113 %l = lshr i32 %x, %p114 %r = icmp eq i32 %l, 2115 ret i1 %r116}117 118; PR43261119 120define i32 @zext_or_eq_ult_add(i32 %i) {121; CHECK-LABEL: @zext_or_eq_ult_add(122; CHECK-NEXT: [[A:%.*]] = add i32 [[I:%.*]], -3123; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A]], 3124; CHECK-NEXT: [[R:%.*]] = zext i1 [[C1]] to i32125; CHECK-NEXT: ret i32 [[R]]126;127 %a = add i32 %i, -3128 %c1 = icmp ult i32 %a, 3129 %c2 = icmp eq i32 %i, 5130 %o = or i1 %c1, %c2131 %r = zext i1 %o to i32132 ret i32 %r133}134 135define i32 @select_zext_or_eq_ult_add(i32 %i) {136; CHECK-LABEL: @select_zext_or_eq_ult_add(137; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3138; CHECK-NEXT: [[NARROW:%.*]] = icmp ult i32 [[TMP1]], 3139; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32140; CHECK-NEXT: ret i32 [[R]]141;142 %a = add i32 %i, -3143 %c1 = icmp ult i32 %a, 2144 %c2 = icmp eq i32 %i, 5145 %z = zext i1 %c2 to i32146 %r = select i1 %c1, i32 1, i32 %z147 ret i32 %r148}149 150; This should not end with more instructions than it started from.151 152define i32 @PR49475(i32 %x, i16 %y) {153; CHECK-LABEL: @PR49475(154; CHECK-NEXT: [[M:%.*]] = and i16 [[Y:%.*]], 1155; CHECK-NEXT: [[B1:%.*]] = icmp eq i32 [[X:%.*]], 0156; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[M]], 0157; CHECK-NEXT: [[T1:%.*]] = or i1 [[B1]], [[B2]]158; CHECK-NEXT: [[Z:%.*]] = zext i1 [[T1]] to i32159; CHECK-NEXT: ret i32 [[Z]]160;161 %m = and i16 %y, 1162 %b1 = icmp eq i32 %x, 0163 %b2 = icmp eq i16 %m, 0164 %t1 = or i1 %b1, %b2165 %z = zext i1 %t1 to i32166 ret i32 %z167}168 169; This would infinite-loop.170 171define i8 @PR49475_infloop(i32 %t0, i16 %insert, i64 %e, i8 %i162) "instcombine-no-verify-fixpoint" {172; CHECK-LABEL: @PR49475_infloop(173; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[INSERT:%.*]], 0174; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0:%.*]], 1175; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP1]], 140176; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64177; CHECK-NEXT: [[XOR:%.*]] = select i1 [[B2]], i64 [[TMP3]], i64 140178; CHECK-NEXT: [[CONV16:%.*]] = sext i8 [[I162:%.*]] to i64179; CHECK-NEXT: [[SUB17:%.*]] = sub i64 [[CONV16]], [[E:%.*]]180; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[SUB17]], 32181; CHECK-NEXT: [[CONV18:%.*]] = ashr exact i64 [[SEXT]], 32182; CHECK-NEXT: [[CMP:%.*]] = icmp sge i64 [[XOR]], [[CONV18]]183; CHECK-NEXT: [[TRUNC44:%.*]] = zext i1 [[CMP]] to i8184; CHECK-NEXT: [[INC:%.*]] = add i8 [[I162]], [[TRUNC44]]185; CHECK-NEXT: [[TOBOOL23_NOT:%.*]] = xor i1 [[CMP]], true186; CHECK-NEXT: call void @llvm.assume(i1 [[TOBOOL23_NOT]])187; CHECK-NEXT: ret i8 [[INC]]188;189 %b = icmp eq i32 %t0, 0190 %b2 = icmp eq i16 %insert, 0191 %t1 = or i1 %b, %b2192 %ext = zext i1 %t1 to i32193 %and = and i32 %t0, %ext194 %conv13 = zext i32 %and to i64195 %xor = xor i64 %conv13, 140196 %conv16 = sext i8 %i162 to i64197 %sub17 = sub i64 %conv16, %e198 %sext = shl i64 %sub17, 32199 %conv18 = ashr exact i64 %sext, 32200 %cmp = icmp sge i64 %xor, %conv18201 %conv19 = zext i1 %cmp to i16202 %or21 = or i16 %insert, %conv19203 %trunc44 = trunc i16 %or21 to i8204 %inc = add i8 %i162, %trunc44205 %tobool23.not = icmp eq i16 %or21, 0206 call void @llvm.assume(i1 %tobool23.not)207 ret i8 %inc208}209 210; This would infinite loop because knownbits changed between checking211; if a transform was profitable and actually doing the transform.212 213define i1 @PR51762(ptr %i, i32 %t0, i16 %t1, ptr %p, ptr %d, ptr %f, i32 %p2, i1 %c1) {214; CHECK-LABEL: @PR51762(215; CHECK-NEXT: entry:216; CHECK-NEXT: br label [[FOR_COND:%.*]]217; CHECK: for.cond:218; CHECK-NEXT: [[I_SROA_8_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[I_SROA_8_0_EXTRACT_TRUNC:%.*]], [[COND_TRUE:%.*]] ]219; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_TRUE]], label [[FOR_END11:%.*]]220; CHECK: cond.true:221; CHECK-NEXT: [[I_SROA_8_0_EXTRACT_TRUNC]] = ashr i32 [[T0:%.*]], 31222; CHECK-NEXT: br label [[FOR_COND]]223; CHECK: for.end11:224; CHECK-NEXT: [[S1:%.*]] = sext i16 [[T1:%.*]] to i64225; CHECK-NEXT: [[SROA38:%.*]] = load i32, ptr [[I:%.*]], align 8226; CHECK-NEXT: [[INSERT_EXT51:%.*]] = zext i32 [[I_SROA_8_0]] to i64227; CHECK-NEXT: [[INSERT_SHIFT52:%.*]] = shl nuw i64 [[INSERT_EXT51]], 32228; CHECK-NEXT: [[INSERT_EXT39:%.*]] = zext i32 [[SROA38]] to i64229; CHECK-NEXT: [[INSERT_INSERT41:%.*]] = or disjoint i64 [[INSERT_SHIFT52]], [[INSERT_EXT39]]230; CHECK-NEXT: [[REM:%.*]] = urem i64 [[S1]], [[INSERT_INSERT41]]231; CHECK-NEXT: [[NE:%.*]] = icmp ne i64 [[REM]], 0232; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[NE]] to i32233; CHECK-NEXT: [[T2:%.*]] = load i32, ptr [[D:%.*]], align 4234; CHECK-NEXT: [[CONV15:%.*]] = sext i16 [[T1]] to i32235; CHECK-NEXT: [[CMP16:%.*]] = icmp sge i32 [[T2]], [[CONV15]]236; CHECK-NEXT: [[CONV17:%.*]] = zext i1 [[CMP16]] to i32237; CHECK-NEXT: [[T3:%.*]] = load i32, ptr [[F:%.*]], align 4238; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[T3]], [[CONV17]]239; CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4240; CHECK-NEXT: [[REM18:%.*]] = srem i32 [[LOR_EXT]], [[ADD]]241; CHECK-NEXT: [[CONV19:%.*]] = zext nneg i32 [[REM18]] to i64242; CHECK-NEXT: store i32 [[SROA38]], ptr [[D]], align 8243; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[INSERT_INSERT41]], [[CONV19]]244; CHECK-NEXT: call void @llvm.assume(i1 [[R]])245; CHECK-NEXT: ret i1 [[R]]246;247entry:248 br label %for.cond249 250for.cond:251 %i.sroa.8.0 = phi i32 [ poison, %entry ], [ %i.sroa.8.0.extract.trunc, %cond.true ]252 br i1 %c1, label %cond.true, label %for.end11253 254cond.true:255 %i.sroa.8.0.extract.trunc = ashr i32 %t0, 31256 br label %for.cond257 258for.end11:259 %s1 = sext i16 %t1 to i64260 %sroa38 = load i32, ptr %i, align 8261 %insert.ext51 = zext i32 %i.sroa.8.0 to i64262 %insert.shift52 = shl nuw i64 %insert.ext51, 32263 %insert.ext39 = zext i32 %sroa38 to i64264 %insert.insert41 = or i64 %insert.shift52, %insert.ext39265 %rem = urem i64 %s1, %insert.insert41266 %ne = icmp ne i64 %rem, 0267 %cmp = icmp eq i64 %insert.insert41, 0268 %spec.select57 = or i1 %ne, %cmp269 270 %lor.ext = zext i1 %spec.select57 to i32271 %t2 = load i32, ptr %d, align 4272 %conv15 = sext i16 %t1 to i32273 %cmp16 = icmp sge i32 %t2, %conv15274 %conv17 = zext i1 %cmp16 to i32275 %t3 = load i32, ptr %f, align 4276 %add = add nsw i32 %t3, %conv17277 store i32 %add, ptr %f, align 4278 %rem18 = srem i32 %lor.ext, %add279 %conv19 = zext i32 %rem18 to i64280 %div = udiv i64 %insert.insert41, %conv19281 %trunc33 = trunc i64 %div to i32282 store i32 %trunc33, ptr %d, align 8283 %r = icmp ult i64 %insert.insert41, %conv19284 call void @llvm.assume(i1 %r)285 ret i1 %r286}287 288declare void @llvm.assume(i1 noundef)289