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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -mtriple=riscv64 -mattr=+zve32x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVE32X3; RUN: opt < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVE64X4; RUN: opt < %s -mtriple=riscv64 -mattr=+zve32x,+zvl128b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVE32X5; RUN: opt < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVE64X6 7define <4 x i1> @load_large_vector(ptr %p) {8; ZVE32X-LABEL: @load_large_vector(9; ZVE32X-NEXT: [[L:%.*]] = load <12 x ptr>, ptr [[P:%.*]], align 12810; ZVE32X-NEXT: [[S1:%.*]] = shufflevector <12 x ptr> [[L]], <12 x ptr> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>11; ZVE32X-NEXT: [[S2:%.*]] = shufflevector <12 x ptr> [[L]], <12 x ptr> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>12; ZVE32X-NEXT: [[RET:%.*]] = icmp ne <4 x ptr> [[S1]], [[S2]]13; ZVE32X-NEXT: ret <4 x i1> [[RET]]14;15; ZVE64X-LABEL: @load_large_vector(16; ZVE64X-NEXT: [[TMP1:%.*]] = call { <4 x ptr>, <4 x ptr>, <4 x ptr> } @llvm.riscv.seg3.load.mask.v4p0.p0.i64(ptr [[P:%.*]], <4 x i1> splat (i1 true), i64 4)17; ZVE64X-NEXT: [[TMP2:%.*]] = extractvalue { <4 x ptr>, <4 x ptr>, <4 x ptr> } [[TMP1]], 118; ZVE64X-NEXT: [[TMP3:%.*]] = extractvalue { <4 x ptr>, <4 x ptr>, <4 x ptr> } [[TMP1]], 019; ZVE64X-NEXT: [[RET:%.*]] = icmp ne <4 x ptr> [[TMP3]], [[TMP2]]20; ZVE64X-NEXT: ret <4 x i1> [[RET]]21;22 %l = load <12 x ptr>, ptr %p23 %s1 = shufflevector <12 x ptr> %l, <12 x ptr> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>24 %s2 = shufflevector <12 x ptr> %l, <12 x ptr> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>25 %ret = icmp ne <4 x ptr> %s1, %s226 ret <4 x i1> %ret27}28