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1; REQUIRES: amdgpu-registered-target && x86-registered-target2; RUN: opt < %s -mtriple=amdgcn -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,DIVERGENT3; RUN: opt < %s -mtriple=x86_64 -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,UNIFORM4 5; Here we assure that for the target with no branch divergence usual Jump Threading optimization performed6; For target with branch divergence - no optimization, so the IR is unchanged.7 8declare i32 @f1()9declare i32 @f2()10declare void @f3()11 12define i32 @test(i1 %cond) {13; CHECK: test14 br i1 %cond, label %T1, label %F115 16; DIVERGENT: T117; UNIFORM-NOT: T118T1:19 %v1 = call i32 @f1()20 br label %Merge21; DIVERGENT: F122; UNIFORM-NOT: F123F1:24 %v2 = call i32 @f2()25 br label %Merge26; DIVERGENT: Merge27; UNIFORM-NOT: Merge28Merge:29 %A = phi i1 [true, %T1], [false, %F1]30 %B = phi i32 [%v1, %T1], [%v2, %F1]31 br i1 %A, label %T2, label %F232 33; DIVERGENT: T234T2:35; UNIFORM: T2:36; UNIFORM: %v1 = call i32 @f1()37; UNIFORM: call void @f3()38; UNIFORM: ret i32 %v139 call void @f3()40 ret i32 %B41; DIVERGENT: F242F2:43; UNIFORM: F2:44; UNIFORM: %v2 = call i32 @f2()45; UNIFORM: ret i32 %v246 ret i32 %B47}48 49; Check divergence check is skipped if there can't be divergence in50; the function.51define i32 @requires_single_lane_exec(i1 %cond) #0 {52; CHECK: requires_single_lane_exec53 br i1 %cond, label %T1, label %F154 55; CHECK-NOT: T156T1:57 %v1 = call i32 @f1()58 br label %Merge59; CHECK-NOT: F160F1:61 %v2 = call i32 @f2()62 br label %Merge63; CHECK-NOT: Merge64Merge:65 %A = phi i1 [true, %T1], [false, %F1]66 %B = phi i32 [%v1, %T1], [%v2, %F1]67 br i1 %A, label %T2, label %F268 69T2:70; CHECK: T2:71; CHECK: %v1 = call i32 @f1()72; CHECK: call void @f3()73; CHECK: ret i32 %v174 call void @f3()75 ret i32 %B76F2:77; CHECK: F2:78; CHECK: %v2 = call i32 @f2()79; CHECK: ret i32 %v280 ret i32 %B81}82 83attributes #0 = { "amdgpu-flat-work-group-size"="1,1" }84