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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S -passes=licm < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define i64 @sve_uaddv(<vscale x 4 x i32> %inv, i1 %c) {7; CHECK-LABEL: define i64 @sve_uaddv(8; CHECK-SAME: <vscale x 4 x i32> [[INV:%.*]], i1 [[C:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: [[UADDV:%.*]] = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[INV]])11; CHECK-NEXT: br label %[[LOOP:.*]]12; CHECK: [[LOOP]]:13; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]14; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 115; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i64 [[IV]], [[UADDV]]16; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false17; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]]18; CHECK: [[EXIT]]:19; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP]] ]20; CHECK-NEXT: ret i64 [[IV_LCSSA]]21;22entry:23 br label %loop24 25loop:26 %iv = phi i64 [ 0, %entry ], [ %iv.next, %cond.true ]27 %iv.next = add i64 %iv, 128 br i1 %c, label %cond.true, label %exit29 30cond.true:31 %uaddv = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %inv)32 %backedge.cond = icmp ult i64 %iv, %uaddv33 br i1 %backedge.cond, label %loop, label %exit34 35exit:36 ret i64 %iv37}38 39define i64 @sve_faddv(<vscale x 4 x float> %inv, i1 %c) {40; CHECK-LABEL: define i64 @sve_faddv(41; CHECK-SAME: <vscale x 4 x float> [[INV:%.*]], i1 [[C:%.*]]) {42; CHECK-NEXT: [[ENTRY:.*]]:43; CHECK-NEXT: br label %[[LOOP:.*]]44; CHECK: [[LOOP]]:45; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]46; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 147; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]48; CHECK: [[COND_TRUE]]:49; CHECK-NEXT: [[FADDV:%.*]] = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[INV]])50; CHECK-NEXT: [[IV_AS_FLOAT:%.*]] = sitofp i64 [[IV]] to float51; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = fcmp olt float [[IV_AS_FLOAT]], [[FADDV]]52; CHECK-NEXT: br i1 [[BACKEDGE_COND]], label %[[LOOP]], label %[[EXIT]]53; CHECK: [[EXIT]]:54; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]55; CHECK-NEXT: ret i64 [[IV_LCSSA]]56;57entry:58 br label %loop59 60loop:61 %iv = phi i64 [ 0, %entry ], [ %iv.next, %cond.true ]62 %iv.next = add i64 %iv, 163 br i1 %c, label %cond.true, label %exit64 65cond.true:66 %faddv = call float @llvm.aarch64.sve.faddv.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> %inv)67 %iv.as.float = sitofp i64 %iv to float68 %backedge.cond = fcmp olt float %iv.as.float, %faddv69 br i1 %backedge.cond, label %loop, label %exit70 71exit:72 ret i64 %iv73}74