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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=licm -verify-memoryssa < %s | FileCheck %s3 4define void @test(ptr %p) {5; CHECK-LABEL: define void @test(6; CHECK-SAME: ptr [[P:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: br label %[[LOOP0:.*]]9; CHECK: [[LOOP0]]:10; CHECK-NEXT: br label %[[LOOP1:.*]]11; CHECK: [[LOOP1]]:12; CHECK-NEXT: [[DEC10:%.*]] = phi i64 [ 0, %[[LOOP0]] ], [ 1, %[[LOOP1]] ]13; CHECK-NEXT: br i1 false, label %[[LOOP1_EXIT:.*]], label %[[LOOP1]]14; CHECK: [[LOOP1_EXIT]]:15; CHECK-NEXT: [[DEC10_LCSSA:%.*]] = phi i64 [ [[DEC10]], %[[LOOP1]] ]16; CHECK-NEXT: switch i32 0, label %[[LOOP0_LATCH:.*]] [17; CHECK-NEXT: i32 0, label %[[LOOP0_LATCH]]18; CHECK-NEXT: i32 2, label %[[LOOP3_PREHEADER:.*]]19; CHECK-NEXT: i32 1, label %[[LOOP2:.*]]20; CHECK-NEXT: ]21; CHECK: [[LOOP2]]:22; CHECK-NEXT: br i1 false, label %[[LOOP0_LATCH]], label %[[LOOP3_PREHEADER]]23; CHECK: [[LOOP3_PREHEADER]]:24; CHECK-NEXT: br label %[[LOOP3:.*]]25; CHECK: [[LOOP3]]:26; CHECK-NEXT: switch i32 0, label %[[EXIT:.*]] [27; CHECK-NEXT: i32 0, label %[[LOOP3]]28; CHECK-NEXT: i32 1, label %[[LOOP2_LATCH:.*]]29; CHECK-NEXT: ]30; CHECK: [[LOOP2_LATCH]]:31; CHECK-NEXT: br label %[[LOOP2]]32; CHECK: [[LOOP0_LATCH]]:33; CHECK-NEXT: br label %[[LOOP0]]34; CHECK: [[EXIT]]:35; CHECK-NEXT: [[DEC10_LCSSA_LCSSA:%.*]] = phi i64 [ [[DEC10_LCSSA]], %[[LOOP3]] ]36; CHECK-NEXT: store i64 [[DEC10_LCSSA_LCSSA]], ptr [[P]], align 437; CHECK-NEXT: store i64 1, ptr [[P]], align 438; CHECK-NEXT: ret void39;40entry:41 br label %loop042 43loop0: ; preds = %loop0.latch, %entry44 br label %loop145 46loop1: ; preds = %loop1, %loop047 %dec10 = phi i64 [ 0, %loop0 ], [ 1, %loop1 ]48 store i64 %dec10, ptr %p49 br i1 false, label %loop1.exit, label %loop150 51loop1.exit: ; preds = %loop152 switch i32 0, label %loop0.latch [53 i32 0, label %loop0.latch54 i32 2, label %loop3.preheader55 i32 1, label %loop256 ]57 58loop2: ; preds = %loop2.latch, %loop1.exit59 br i1 false, label %loop0.latch, label %loop3.preheader60 61loop3.preheader: ; preds = %loop1.exit, %loop262 br label %loop363 64loop3: ; preds = %loop3.preheader, %loop365 switch i32 0, label %exit [66 i32 0, label %loop367 i32 1, label %loop2.latch68 ]69 70loop2.latch: ; preds = %loop371 br label %loop272 73loop0.latch: ; preds = %loop2, %loop1.exit, %loop1.exit74 store i64 0, ptr %p75 br label %loop076 77exit: ; preds = %loop378 store i64 1, ptr %p79 ret void80}81