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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=licm -S -verify-memoryssa | FileCheck %s3 4target datalayout = "n64"5 6declare i32 @strlen(ptr) readonly nounwind willreturn7 8declare void @foo()9 10; Sink readonly function.11define i32 @test1(ptr %P) {12; CHECK-LABEL: @test1(13; CHECK-NEXT: br label [[LOOP:%.*]]14; CHECK: Loop:15; CHECK-NEXT: br i1 false, label [[LOOP]], label [[OUT:%.*]]16; CHECK: Out:17; CHECK-NEXT: [[A_LE:%.*]] = call i32 @strlen(ptr [[P:%.*]]) #[[ATTR3:[0-9]+]]18; CHECK-NEXT: ret i32 [[A_LE]]19;20 br label %Loop21 22Loop: ; preds = %Loop, %023 %A = call i32 @strlen( ptr %P ) readonly24 br i1 false, label %Loop, label %Out25 26Out: ; preds = %Loop27 ret i32 %A28}29 30declare double @sin(double) readnone nounwind willreturn31 32; Sink readnone function out of loop with unknown memory behavior.33define double @test2(double %X) {34; CHECK-LABEL: @test2(35; CHECK-NEXT: br label [[LOOP:%.*]]36; CHECK: Loop:37; CHECK-NEXT: call void @foo()38; CHECK-NEXT: br i1 true, label [[LOOP]], label [[OUT:%.*]]39; CHECK: Out:40; CHECK-NEXT: [[A_LE:%.*]] = call double @sin(double [[X:%.*]]) #[[ATTR4:[0-9]+]]41; CHECK-NEXT: ret double [[A_LE]]42;43 br label %Loop44 45Loop: ; preds = %Loop, %046 call void @foo( )47 %A = call double @sin( double %X ) readnone48 br i1 true, label %Loop, label %Out49 50Out: ; preds = %Loop51 ret double %A52}53 54; FIXME: Should be able to sink this case55define i32 @test2b(i32 %X) {56; CHECK-LABEL: @test2b(57; CHECK-NEXT: br label [[LOOP:%.*]]58; CHECK: Loop:59; CHECK-NEXT: call void @foo()60; CHECK-NEXT: br i1 true, label [[LOOP]], label [[OUT:%.*]]61; CHECK: Out:62; CHECK-NEXT: [[A_LE:%.*]] = sdiv i32 10, [[X:%.*]]63; CHECK-NEXT: ret i32 [[A_LE]]64;65 br label %Loop66 67Loop: ; preds = %Loop, %068 call void @foo( )69 %A = sdiv i32 10, %X70 br i1 true, label %Loop, label %Out71 72Out: ; preds = %Loop73 ret i32 %A74}75 76define double @test2c(ptr %P) {77; CHECK-LABEL: @test2c(78; CHECK-NEXT: br label [[LOOP:%.*]]79; CHECK: Loop:80; CHECK-NEXT: call void @foo()81; CHECK-NEXT: br i1 true, label [[LOOP]], label [[OUT:%.*]]82; CHECK: Out:83; CHECK-NEXT: [[A_LE:%.*]] = load double, ptr [[P:%.*]], align 8, !invariant.load !084; CHECK-NEXT: ret double [[A_LE]]85;86 br label %Loop87 88Loop: ; preds = %Loop, %089 call void @foo( )90 %A = load double, ptr %P, !invariant.load !{}91 br i1 true, label %Loop, label %Out92 93Out: ; preds = %Loop94 ret double %A95}96 97; This testcase checks to make sure the sinker does not cause problems with98; critical edges.99define void @test3() {100; CHECK-LABEL: @test3(101; CHECK-NEXT: Entry:102; CHECK-NEXT: br i1 false, label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]103; CHECK: Loop.preheader:104; CHECK-NEXT: br label [[LOOP:%.*]]105; CHECK: Loop:106; CHECK-NEXT: br i1 false, label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]]107; CHECK: Exit.loopexit:108; CHECK-NEXT: [[X_LE:%.*]] = add i32 0, 1109; CHECK-NEXT: br label [[EXIT]]110; CHECK: Exit:111; CHECK-NEXT: [[Y:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[X_LE]], [[EXIT_LOOPEXIT]] ]112; CHECK-NEXT: ret void113;114Entry:115 br i1 false, label %Loop, label %Exit116Loop:117 %X = add i32 0, 1118 br i1 false, label %Loop, label %Exit119Exit:120 %Y = phi i32 [ 0, %Entry ], [ %X, %Loop ]121 ret void122 123 124}125 126; If the result of an instruction is only used outside of the loop, sink127; the instruction to the exit blocks instead of executing it on every128; iteration of the loop.129;130define i32 @test4(i32 %N) {131; CHECK-LABEL: @test4(132; CHECK-NEXT: Entry:133; CHECK-NEXT: br label [[LOOP:%.*]]134; CHECK: Loop:135; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[LOOP]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]136; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1137; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1138; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT:%.*]]139; CHECK: Out:140; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]141; CHECK-NEXT: [[TMP_6_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]142; CHECK-NEXT: [[TMP_7_LE:%.*]] = sub i32 [[TMP_6_LE]], [[N]]143; CHECK-NEXT: ret i32 [[TMP_7_LE]]144;145Entry:146 br label %Loop147Loop: ; preds = %Loop, %Entry148 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]149 %tmp.6 = mul i32 %N, %N_addr.0.pn ; <i32> [#uses=1]150 %tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=1]151 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]152 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1]153 br i1 %tmp.1, label %Loop, label %Out154Out: ; preds = %Loop155 ret i32 %tmp.7156}157 158; To reduce register pressure, if a load is hoistable out of the loop, and the159; result of the load is only used outside of the loop, sink the load instead of160; hoisting it!161;162@X = global i32 5 ; <ptr> [#uses=1]163 164define i32 @test5(i32 %N) {165; CHECK-LABEL: @test5(166; CHECK-NEXT: Entry:167; CHECK-NEXT: br label [[LOOP:%.*]]168; CHECK: Loop:169; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[LOOP]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]170; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1171; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1172; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT:%.*]]173; CHECK: Out:174; CHECK-NEXT: [[TMP_6_LE:%.*]] = load i32, ptr @X, align 4175; CHECK-NEXT: ret i32 [[TMP_6_LE]]176;177Entry:178 br label %Loop179Loop: ; preds = %Loop, %Entry180 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]181 %tmp.6 = load i32, ptr @X ; <i32> [#uses=1]182 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]183 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1]184 br i1 %tmp.1, label %Loop, label %Out185Out: ; preds = %Loop186 ret i32 %tmp.6187}188 189 190 191; The loop sinker was running from the bottom of the loop to the top, causing192; it to miss opportunities to sink instructions that depended on sinking other193; instructions from the loop. Instead they got hoisted, which is better than194; leaving them in the loop, but increases register pressure pointlessly.195 196 %Ty = type { i32, i32 }197@X2 = external global %Ty198 199define i32 @test6() {200; CHECK-LABEL: @test6(201; CHECK-NEXT: br label [[LOOP:%.*]]202; CHECK: Loop:203; CHECK-NEXT: br i1 false, label [[LOOP]], label [[OUT:%.*]]204; CHECK: Out:205; CHECK-NEXT: [[SUNK2_LE:%.*]] = load i32, ptr @X2, align 4206; CHECK-NEXT: ret i32 [[SUNK2_LE]]207;208 br label %Loop209Loop:210 %sunk2 = load i32, ptr @X2211 br i1 false, label %Loop, label %Out212Out: ; preds = %Loop213 ret i32 %sunk2214}215 216 217 218; This testcase ensures that we can sink instructions from loops with219; multiple exits.220;221define i32 @test7(i32 %N, i1 %C) {222; CHECK-LABEL: @test7(223; CHECK-NEXT: Entry:224; CHECK-NEXT: br label [[LOOP:%.*]]225; CHECK: Loop:226; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]227; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1228; CHECK-NEXT: br i1 [[C:%.*]], label [[CONTLOOP]], label [[OUT1:%.*]]229; CHECK: ContLoop:230; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1231; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT2:%.*]]232; CHECK: Out1:233; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]234; CHECK-NEXT: [[TMP_6_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]235; CHECK-NEXT: [[TMP_7_LE2:%.*]] = sub i32 [[TMP_6_LE]], [[N]]236; CHECK-NEXT: ret i32 [[TMP_7_LE2]]237; CHECK: Out2:238; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA5:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP]] ]239; CHECK-NEXT: [[TMP_6_LE4:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA5]]240; CHECK-NEXT: [[TMP_7_LE:%.*]] = sub i32 [[TMP_6_LE4]], [[N]]241; CHECK-NEXT: ret i32 [[TMP_7_LE]]242;243Entry:244 br label %Loop245Loop: ; preds = %ContLoop, %Entry246 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]247 %tmp.6 = mul i32 %N, %N_addr.0.pn248 %tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=2]249 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]250 br i1 %C, label %ContLoop, label %Out1251ContLoop:252 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1253 br i1 %tmp.1, label %Loop, label %Out2254Out1: ; preds = %Loop255 ret i32 %tmp.7256Out2: ; preds = %ContLoop257 ret i32 %tmp.7258}259 260 261; This testcase checks to make sure we can sink values which are only live on262; some exits out of the loop, and that we can do so without breaking dominator263; info.264define i32 @test8(i1 %C1, i1 %C2, ptr %P, ptr %Q) {265; CHECK-LABEL: @test8(266; CHECK-NEXT: Entry:267; CHECK-NEXT: br label [[LOOP:%.*]]268; CHECK: Loop:269; CHECK-NEXT: br i1 [[C1:%.*]], label [[CONT:%.*]], label [[EXIT1:%.*]]270; CHECK: Cont:271; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 4272; CHECK-NEXT: store i32 [[X]], ptr [[Q:%.*]], align 4273; CHECK-NEXT: br i1 [[C2:%.*]], label [[LOOP]], label [[EXIT2:%.*]]274; CHECK: exit1:275; CHECK-NEXT: ret i32 0276; CHECK: exit2:277; CHECK-NEXT: [[X_LCSSA:%.*]] = phi i32 [ [[X]], [[CONT]] ]278; CHECK-NEXT: [[V_LE:%.*]] = add i32 [[X_LCSSA]], 1279; CHECK-NEXT: ret i32 [[V_LE]]280;281Entry:282 br label %Loop283Loop: ; preds = %Cont, %Entry284 br i1 %C1, label %Cont, label %exit1285Cont: ; preds = %Loop286 %X = load i32, ptr %P ; <i32> [#uses=2]287 store i32 %X, ptr %Q288 %V = add i32 %X, 1 ; <i32> [#uses=1]289 br i1 %C2, label %Loop, label %exit2290exit1: ; preds = %Loop291 ret i32 0292exit2: ; preds = %Cont293 ret i32 %V294}295 296 297define void @test9() {298; CHECK-LABEL: @test9(299; CHECK-NEXT: loopentry.2.i:300; CHECK-NEXT: br i1 false, label [[NO_EXIT_1_I_PREHEADER:%.*]], label [[LOOPENTRY_3_I_PREHEADER:%.*]]301; CHECK: no_exit.1.i.preheader:302; CHECK-NEXT: br label [[NO_EXIT_1_I:%.*]]303; CHECK: no_exit.1.i:304; CHECK-NEXT: br i1 false, label [[RETURN_I:%.*]], label [[ENDIF_8_I:%.*]]305; CHECK: endif.8.i:306; CHECK-NEXT: br i1 false, label [[NO_EXIT_1_I]], label [[LOOPENTRY_3_I_PREHEADER_LOOPEXIT:%.*]]307; CHECK: loopentry.3.i.preheader.loopexit:308; CHECK-NEXT: [[INC_1_I_LE:%.*]] = add i32 0, 1309; CHECK-NEXT: br label [[LOOPENTRY_3_I_PREHEADER]]310; CHECK: loopentry.3.i.preheader:311; CHECK-NEXT: [[ARG_NUM_0_I_PH13000:%.*]] = phi i32 [ 0, [[LOOPENTRY_2_I:%.*]] ], [ [[INC_1_I_LE]], [[LOOPENTRY_3_I_PREHEADER_LOOPEXIT]] ]312; CHECK-NEXT: ret void313; CHECK: return.i:314; CHECK-NEXT: ret void315;316loopentry.2.i:317 br i1 false, label %no_exit.1.i.preheader, label %loopentry.3.i.preheader318no_exit.1.i.preheader: ; preds = %loopentry.2.i319 br label %no_exit.1.i320no_exit.1.i: ; preds = %endif.8.i, %no_exit.1.i.preheader321 br i1 false, label %return.i, label %endif.8.i322endif.8.i: ; preds = %no_exit.1.i323 %inc.1.i = add i32 0, 1 ; <i32> [#uses=1]324 br i1 false, label %no_exit.1.i, label %loopentry.3.i.preheader.loopexit325loopentry.3.i.preheader.loopexit: ; preds = %endif.8.i326 br label %loopentry.3.i.preheader327loopentry.3.i.preheader: ; preds = %loopentry.3.i.preheader.loopexit, %loopentry.2.i328 %arg_num.0.i.ph13000 = phi i32 [ 0, %loopentry.2.i ], [ %inc.1.i, %loopentry.3.i.preheader.loopexit ] ; <i32> [#uses=0]329 ret void330return.i: ; preds = %no_exit.1.i331 ret void332 333}334 335 336; Potentially trapping instructions may be sunk as long as they are guaranteed337; to be executed.338define i32 @test10(i32 %N) {339; CHECK-LABEL: @test10(340; CHECK-NEXT: Entry:341; CHECK-NEXT: br label [[LOOP:%.*]]342; CHECK: Loop:343; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[LOOP]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]344; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1345; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 0346; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT:%.*]]347; CHECK: Out:348; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]349; CHECK-NEXT: [[TMP_6_LE:%.*]] = sdiv i32 [[N]], [[N_ADDR_0_PN_LCSSA]]350; CHECK-NEXT: ret i32 [[TMP_6_LE]]351;352Entry:353 br label %Loop354Loop: ; preds = %Loop, %Entry355 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ] ; <i32> [#uses=3]356 %tmp.6 = sdiv i32 %N, %N_addr.0.pn ; <i32> [#uses=1]357 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1]358 %tmp.1 = icmp ne i32 %N_addr.0.pn, 0 ; <i1> [#uses=1]359 br i1 %tmp.1, label %Loop, label %Out360Out: ; preds = %Loop361 ret i32 %tmp.6362 363}364 365; Should delete, not sink, dead instructions.366define void @test11() {367; CHECK-LABEL: @test11(368; CHECK-NEXT: br label [[LOOP:%.*]]369; CHECK: Loop:370; CHECK-NEXT: br i1 false, label [[LOOP]], label [[OUT:%.*]]371; CHECK: Out:372; CHECK-NEXT: ret void373;374 br label %Loop375Loop:376 %dead2 = getelementptr %Ty, ptr @X2, i64 0, i32 1377 br i1 false, label %Loop, label %Out378Out:379 ret void380}381 382@c = common global [1 x i32] zeroinitializer, align 4383 384; Test a *many* way nested loop with multiple exit blocks both of which exit385; multiple loop nests. This exercises LCSSA corner cases.386define i32 @PR18753(ptr %a, ptr %b, ptr %c, ptr %d) {387; CHECK-LABEL: @PR18753(388; CHECK-NEXT: entry:389; CHECK-NEXT: br label [[L1_HEADER:%.*]]390; CHECK: l1.header:391; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[L1_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]392; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [1 x i32], ptr @c, i64 0, i64 [[IV]]393; CHECK-NEXT: br label [[L2_HEADER:%.*]]394; CHECK: l2.header:395; CHECK-NEXT: [[X0:%.*]] = load i1, ptr [[C:%.*]], align 4396; CHECK-NEXT: br i1 [[X0]], label [[L1_LATCH]], label [[L3_PREHEADER:%.*]]397; CHECK: l3.preheader:398; CHECK-NEXT: br label [[L3_HEADER:%.*]]399; CHECK: l3.header:400; CHECK-NEXT: [[X1:%.*]] = load i1, ptr [[D:%.*]], align 4401; CHECK-NEXT: br i1 [[X1]], label [[L2_LATCH:%.*]], label [[L4_PREHEADER:%.*]]402; CHECK: l4.preheader:403; CHECK-NEXT: br label [[L4_HEADER:%.*]]404; CHECK: l4.header:405; CHECK-NEXT: [[X2:%.*]] = load i1, ptr [[A:%.*]], align 1406; CHECK-NEXT: br i1 [[X2]], label [[L3_LATCH:%.*]], label [[L4_BODY:%.*]]407; CHECK: l4.body:408; CHECK-NEXT: call void @f(ptr [[ARRAYIDX_I]])409; CHECK-NEXT: [[X3:%.*]] = load i1, ptr [[B:%.*]], align 1410; CHECK-NEXT: br i1 [[X3]], label [[L4_LATCH:%.*]], label [[EXIT:%.*]]411; CHECK: l4.latch:412; CHECK-NEXT: call void @g()413; CHECK-NEXT: [[X4:%.*]] = load i1, ptr [[B]], align 4414; CHECK-NEXT: br i1 [[X4]], label [[L4_HEADER]], label [[EXIT]]415; CHECK: l3.latch:416; CHECK-NEXT: br label [[L3_HEADER]]417; CHECK: l2.latch:418; CHECK-NEXT: br label [[L2_HEADER]]419; CHECK: l1.latch:420; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1421; CHECK-NEXT: br label [[L1_HEADER]]422; CHECK: exit:423; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], [[L4_LATCH]] ], [ [[IV]], [[L4_BODY]] ]424; CHECK-NEXT: [[L_LE:%.*]] = trunc i64 [[IV_LCSSA]] to i32425; CHECK-NEXT: ret i32 [[L_LE]]426;427entry:428 br label %l1.header429 430l1.header:431 %iv = phi i64 [ %iv.next, %l1.latch ], [ 0, %entry ]432 %arrayidx.i = getelementptr inbounds [1 x i32], ptr @c, i64 0, i64 %iv433 br label %l2.header434 435l2.header:436 %x0 = load i1, ptr %c, align 4437 br i1 %x0, label %l1.latch, label %l3.preheader438 439l3.preheader:440 br label %l3.header441 442l3.header:443 %x1 = load i1, ptr %d, align 4444 br i1 %x1, label %l2.latch, label %l4.preheader445 446l4.preheader:447 br label %l4.header448 449l4.header:450 %x2 = load i1, ptr %a451 br i1 %x2, label %l3.latch, label %l4.body452 453l4.body:454 call void @f(ptr %arrayidx.i)455 %x3 = load i1, ptr %b456 %l = trunc i64 %iv to i32457 br i1 %x3, label %l4.latch, label %exit458 459l4.latch:460 call void @g()461 %x4 = load i1, ptr %b, align 4462 br i1 %x4, label %l4.header, label %exit463 464l3.latch:465 br label %l3.header466 467l2.latch:468 br label %l2.header469 470l1.latch:471 %iv.next = add nsw i64 %iv, 1472 br label %l1.header473 474exit:475 %lcssa = phi i32 [ %l, %l4.latch ], [ %l, %l4.body ]476 477 ret i32 %lcssa478}479 480; @test12 moved to sink-promote.ll, as it tests sinking and promotion.481 482; Test that we don't crash when trying to sink stores and there's no preheader483; available (which is used for creating loads that may be used by the SSA484; updater)485define void @test13(i1 %arg) {486; CHECK-LABEL: @test13(487; CHECK-NEXT: br label [[LAB59:%.*]]488; CHECK: lab19:489; CHECK-NEXT: br i1 [[ARG:%.*]], label [[LAB20:%.*]], label [[LAB38_LOOPEXIT:%.*]]490; CHECK: lab20:491; CHECK-NEXT: br label [[LAB60:%.*]]492; CHECK: lab21:493; CHECK-NEXT: br i1 [[ARG]], label [[LAB22:%.*]], label [[LAB38:%.*]]494; CHECK: lab22:495; CHECK-NEXT: br label [[LAB38]]496; CHECK: lab38.loopexit:497; CHECK-NEXT: br label [[LAB38]]498; CHECK: lab38:499; CHECK-NEXT: ret void500; CHECK: lab59:501; CHECK-NEXT: indirectbr ptr undef, [label [[LAB60]], label %lab38]502; CHECK: lab60:503; CHECK-NEXT: store i32 2145244101, ptr undef, align 4504; CHECK-NEXT: indirectbr ptr undef, [label [[LAB21:%.*]], label %lab19]505;506 br label %lab59507 508lab19:509 br i1 %arg, label %lab20, label %lab38510 511lab20:512 br label %lab60513 514lab21:515 br i1 %arg, label %lab22, label %lab38516 517lab22:518 br label %lab38519 520lab38:521 ret void522 523lab59:524 indirectbr ptr undef, [label %lab60, label %lab38]525 526lab60:527 store i32 2145244101, ptr undef, align 4528 indirectbr ptr undef, [label %lab21, label %lab19]529}530 531; Check if LICM can sink a sinkable instruction the exit blocks through532; a non-trivially replacable PHI node.533define i32 @test14(i32 %N, i32 %N2, i1 %C) {534; CHECK-LABEL: @test14(535; CHECK-NEXT: Entry:536; CHECK-NEXT: br label [[LOOP:%.*]]537; CHECK: Loop:538; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]539; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1540; CHECK-NEXT: br i1 [[C:%.*]], label [[CONTLOOP]], label [[OUT12_SPLIT_LOOP_EXIT1:%.*]]541; CHECK: ContLoop:542; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1543; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT12_SPLIT_LOOP_EXIT:%.*]]544; CHECK: Out12.split.loop.exit:545; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA4:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP]] ]546; CHECK-NEXT: [[SINK_MUL_LE3:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA4]]547; CHECK-NEXT: br label [[OUT12:%.*]]548; CHECK: Out12.split.loop.exit1:549; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]550; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]551; CHECK-NEXT: [[SINK_SUB_LE:%.*]] = sub i32 [[SINK_MUL_LE]], [[N]]552; CHECK-NEXT: br label [[OUT12]]553; CHECK: Out12:554; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[SINK_MUL_LE3]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]555; CHECK-NEXT: ret i32 [[TMP]]556;557Entry:558 br label %Loop559Loop:560 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]561 %sink.mul = mul i32 %N, %N_addr.0.pn562 %sink.sub = sub i32 %sink.mul, %N563 %dec = add i32 %N_addr.0.pn, -1564 br i1 %C, label %ContLoop, label %Out12565ContLoop:566 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1567 br i1 %tmp.1, label %Loop, label %Out12568Out12:569 %tmp = phi i32 [%sink.mul, %ContLoop], [%sink.sub, %Loop]570 ret i32 %tmp571}572 573; In this test, splitting predecessors is not really required because the574; operations of sinkable instructions (sub and mul) are same. In this case, we575; can sink the same sinkable operations and modify the PHI to pass the operands576; to the shared operations. As of now, we split predecessors of non-trivially577; replicalbe PHIs by default in LICM because all incoming edges of a578; non-trivially replacable PHI in LCSSA is critical.579define i32 @test15(i32 %N, i32 %N2, i1 %C) {580; CHECK-LABEL: @test15(581; CHECK-NEXT: Entry:582; CHECK-NEXT: br label [[LOOP:%.*]]583; CHECK: Loop:584; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]585; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1586; CHECK-NEXT: br i1 [[C:%.*]], label [[CONTLOOP]], label [[OUT12_SPLIT_LOOP_EXIT1:%.*]]587; CHECK: ContLoop:588; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1589; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT12_SPLIT_LOOP_EXIT:%.*]]590; CHECK: Out12.split.loop.exit:591; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA5:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP]] ]592; CHECK-NEXT: [[SINK_MUL_LE4:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA5]]593; CHECK-NEXT: [[SINK_SUB2_LE:%.*]] = sub i32 [[SINK_MUL_LE4]], [[N2:%.*]]594; CHECK-NEXT: br label [[OUT12:%.*]]595; CHECK: Out12.split.loop.exit1:596; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]597; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]598; CHECK-NEXT: [[SINK_SUB_LE:%.*]] = sub i32 [[SINK_MUL_LE]], [[N]]599; CHECK-NEXT: br label [[OUT12]]600; CHECK: Out12:601; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[SINK_SUB2_LE]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]602; CHECK-NEXT: ret i32 [[TMP]]603;604Entry:605 br label %Loop606Loop:607 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]608 %sink.mul = mul i32 %N, %N_addr.0.pn609 %sink.sub = sub i32 %sink.mul, %N610 %sink.sub2 = sub i32 %sink.mul, %N2611 %dec = add i32 %N_addr.0.pn, -1612 br i1 %C, label %ContLoop, label %Out12613ContLoop:614 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1615 br i1 %tmp.1, label %Loop, label %Out12616Out12:617 %tmp = phi i32 [%sink.sub2, %ContLoop], [%sink.sub, %Loop]618 ret i32 %tmp619}620 621; Sink through a non-trivially replacable PHI node which use the same sinkable622; instruction multiple times.623define i32 @test16(i1 %c, ptr %P, ptr %P2, i64 %V) {624; CHECK-LABEL: @test16(625; CHECK-NEXT: entry:626; CHECK-NEXT: br label [[LOOP_PH:%.*]]627; CHECK: loop.ph:628; CHECK-NEXT: br label [[LOOP:%.*]]629; CHECK: Loop:630; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[LOOP_PH]] ], [ [[NEXT:%.*]], [[CONTLOOP:%.*]] ]631; CHECK-NEXT: [[L2:%.*]] = call i32 @getv()632; CHECK-NEXT: switch i32 [[L2]], label [[CONTLOOP]] [633; CHECK-NEXT: i32 32, label [[OUT_SPLIT_LOOP_EXIT1:%.*]]634; CHECK-NEXT: i32 46, label [[OUT_SPLIT_LOOP_EXIT1]]635; CHECK-NEXT: i32 95, label [[OUT_SPLIT_LOOP_EXIT1]]636; CHECK-NEXT: ]637; CHECK: ContLoop:638; CHECK-NEXT: [[NEXT]] = add nuw i64 [[IV]], 1639; CHECK-NEXT: [[C1:%.*]] = call i1 @getc()640; CHECK-NEXT: br i1 [[C1]], label [[LOOP]], label [[OUT_SPLIT_LOOP_EXIT:%.*]]641; CHECK: Out.split.loop.exit:642; CHECK-NEXT: [[IDX_PH:%.*]] = phi i32 [ [[L2]], [[CONTLOOP]] ]643; CHECK-NEXT: br label [[OUT:%.*]]644; CHECK: Out.split.loop.exit1:645; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], [[LOOP]] ], [ [[IV]], [[LOOP]] ], [ [[IV]], [[LOOP]] ]646; CHECK-NEXT: [[L2_LCSSA:%.*]] = phi i32 [ [[L2]], [[LOOP]] ], [ [[L2]], [[LOOP]] ], [ [[L2]], [[LOOP]] ]647; CHECK-NEXT: [[T_LE:%.*]] = trunc i64 [[IV_LCSSA]] to i32648; CHECK-NEXT: [[SINKABLE_LE:%.*]] = mul i32 [[L2_LCSSA]], [[T_LE]]649; CHECK-NEXT: br label [[OUT]]650; CHECK: Out:651; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_PH]], [[OUT_SPLIT_LOOP_EXIT]] ], [ [[SINKABLE_LE]], [[OUT_SPLIT_LOOP_EXIT1]] ]652; CHECK-NEXT: ret i32 [[IDX]]653;654entry:655 br label %loop.ph656loop.ph:657 br label %Loop658Loop:659 %iv = phi i64 [ 0, %loop.ph ], [ %next, %ContLoop ]660 %l2 = call i32 @getv()661 %t = trunc i64 %iv to i32662 %sinkable = mul i32 %l2, %t663 switch i32 %l2, label %ContLoop [664 i32 32, label %Out665 i32 46, label %Out666 i32 95, label %Out667 ]668ContLoop:669 %next = add nuw i64 %iv, 1670 %c1 = call i1 @getc()671 br i1 %c1, label %Loop, label %Out672Out:673 %idx = phi i32 [ %l2, %ContLoop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ]674 ret i32 %idx675}676 677; Sink a sinkable instruction through multiple non-trivially replacable PHIs in678; differect exit blocks.679define i32 @test17(i32 %N, i32 %N2) {680; CHECK-LABEL: @test17(681; CHECK-NEXT: Entry:682; CHECK-NEXT: br label [[LOOP:%.*]]683; CHECK: Loop:684; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP3:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]685; CHECK-NEXT: [[C0:%.*]] = call i1 @getc()686; CHECK-NEXT: br i1 [[C0]], label [[CONTLOOP1:%.*]], label [[OUTA_SPLIT_LOOP_EXIT3:%.*]]687; CHECK: ContLoop1:688; CHECK-NEXT: [[C1:%.*]] = call i1 @getc()689; CHECK-NEXT: br i1 [[C1]], label [[CONTLOOP2:%.*]], label [[OUTA_SPLIT_LOOP_EXIT:%.*]]690; CHECK: ContLoop2:691; CHECK-NEXT: [[C2:%.*]] = call i1 @getc()692; CHECK-NEXT: br i1 [[C2]], label [[CONTLOOP3]], label [[OUTB_SPLIT_LOOP_EXIT1:%.*]]693; CHECK: ContLoop3:694; CHECK-NEXT: [[C3:%.*]] = call i1 @getc()695; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1696; CHECK-NEXT: br i1 [[C3]], label [[LOOP]], label [[OUTB_SPLIT_LOOP_EXIT:%.*]]697; CHECK: OutA.split.loop.exit:698; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP1]] ]699; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]700; CHECK-NEXT: br label [[OUTA:%.*]]701; CHECK: OutA.split.loop.exit3:702; CHECK-NEXT: [[TMP1_PH4:%.*]] = phi i32 [ [[N2:%.*]], [[LOOP]] ]703; CHECK-NEXT: br label [[OUTA]]704; CHECK: OutA:705; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[SINK_MUL_LE]], [[OUTA_SPLIT_LOOP_EXIT]] ], [ [[TMP1_PH4]], [[OUTA_SPLIT_LOOP_EXIT3]] ]706; CHECK-NEXT: br label [[OUT12:%.*]]707; CHECK: OutB.split.loop.exit:708; CHECK-NEXT: [[TMP2_PH:%.*]] = phi i32 [ [[DEC]], [[CONTLOOP3]] ]709; CHECK-NEXT: br label [[OUTB:%.*]]710; CHECK: OutB.split.loop.exit1:711; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA6:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP2]] ]712; CHECK-NEXT: [[SINK_MUL_LE5:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA6]]713; CHECK-NEXT: br label [[OUTB]]714; CHECK: OutB:715; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[TMP2_PH]], [[OUTB_SPLIT_LOOP_EXIT]] ], [ [[SINK_MUL_LE5]], [[OUTB_SPLIT_LOOP_EXIT1]] ]716; CHECK-NEXT: br label [[OUT12]]717; CHECK: Out12:718; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[TMP1]], [[OUTA]] ], [ [[TMP2]], [[OUTB]] ]719; CHECK-NEXT: ret i32 [[TMP]]720;721Entry:722 br label %Loop723Loop:724 %N_addr.0.pn = phi i32 [ %dec, %ContLoop3 ], [ %N, %Entry ]725 %sink.mul = mul i32 %N, %N_addr.0.pn726 %c0 = call i1 @getc()727 br i1 %c0 , label %ContLoop1, label %OutA728ContLoop1:729 %c1 = call i1 @getc()730 br i1 %c1, label %ContLoop2, label %OutA731 732ContLoop2:733 %c2 = call i1 @getc()734 br i1 %c2, label %ContLoop3, label %OutB735ContLoop3:736 %c3 = call i1 @getc()737 %dec = add i32 %N_addr.0.pn, -1738 br i1 %c3, label %Loop, label %OutB739OutA:740 %tmp1 = phi i32 [%sink.mul, %ContLoop1], [%N2, %Loop]741 br label %Out12742OutB:743 %tmp2 = phi i32 [%sink.mul, %ContLoop2], [%dec, %ContLoop3]744 br label %Out12745Out12:746 %tmp = phi i32 [%tmp1, %OutA], [%tmp2, %OutB]747 ret i32 %tmp748}749 750 751; Sink a sinkable instruction through both trivially and non-trivially replacable PHIs.752define i32 @test18(i32 %N, i32 %N2) {753; CHECK-LABEL: @test18(754; CHECK-NEXT: Entry:755; CHECK-NEXT: br label [[LOOP:%.*]]756; CHECK: Loop:757; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]758; CHECK-NEXT: [[C0:%.*]] = call i1 @getc()759; CHECK-NEXT: br i1 [[C0]], label [[CONTLOOP]], label [[OUT12_SPLIT_LOOP_EXIT1:%.*]]760; CHECK: ContLoop:761; CHECK-NEXT: [[DEC]] = add i32 [[IV]], -1762; CHECK-NEXT: [[C1:%.*]] = call i1 @getc()763; CHECK-NEXT: br i1 [[C1]], label [[LOOP]], label [[OUT12_SPLIT_LOOP_EXIT:%.*]]764; CHECK: Out12.split.loop.exit:765; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[CONTLOOP]] ]766; CHECK-NEXT: [[TMP2_PH:%.*]] = phi i32 [ [[DEC]], [[CONTLOOP]] ]767; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[IV_LCSSA]]768; CHECK-NEXT: [[SINK_SUB_LE4:%.*]] = sub i32 [[SINK_MUL_LE]], [[N2:%.*]]769; CHECK-NEXT: br label [[OUT12:%.*]]770; CHECK: Out12.split.loop.exit1:771; CHECK-NEXT: [[IV_LCSSA7:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]772; CHECK-NEXT: [[SINK_MUL_LE6:%.*]] = mul i32 [[N]], [[IV_LCSSA7]]773; CHECK-NEXT: [[SINK_SUB_LE:%.*]] = sub i32 [[SINK_MUL_LE6]], [[N2]]774; CHECK-NEXT: br label [[OUT12]]775; CHECK: Out12:776; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[SINK_SUB_LE4]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]777; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[TMP2_PH]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]778; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[TMP2]]779; CHECK-NEXT: ret i32 [[ADD]]780;781Entry:782 br label %Loop783Loop:784 %iv = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ]785 %sink.mul = mul i32 %N, %iv786 %sink.sub = sub i32 %sink.mul, %N2787 %c0 = call i1 @getc()788 br i1 %c0, label %ContLoop, label %Out12789ContLoop:790 %dec = add i32 %iv, -1791 %c1 = call i1 @getc()792 br i1 %c1, label %Loop, label %Out12793Out12:794 %tmp1 = phi i32 [%sink.sub, %ContLoop], [%sink.sub, %Loop]795 %tmp2 = phi i32 [%dec, %ContLoop], [%sink.sub, %Loop]796 %add = add i32 %tmp1, %tmp2797 ret i32 %add798}799 800; Do not sink an instruction through a non-trivially replacable PHI, to avoid801; assert while splitting predecessors, if the terminator of predecessor is an802; indirectbr.803define i32 @test19(i1 %cond, i1 %cond2, ptr %address, i32 %v1) nounwind {804; CHECK-LABEL: @test19(805; CHECK-NEXT: entry:806; CHECK-NEXT: [[INDIRECT_GOTO_DEST:%.*]] = select i1 [[COND:%.*]], ptr blockaddress(@test19, [[EXIT:%.*]]), ptr [[ADDRESS:%.*]]807; CHECK-NEXT: [[INDIRECT_GOTO_DEST2:%.*]] = select i1 [[COND2:%.*]], ptr blockaddress(@test19, [[EXIT]]), ptr [[ADDRESS]]808; CHECK-NEXT: br label [[L0:%.*]]809; CHECK: L0:810; CHECK-NEXT: [[V2:%.*]] = call i32 @getv()811; CHECK-NEXT: [[SINKABLE:%.*]] = mul i32 [[V1:%.*]], [[V2]]812; CHECK-NEXT: [[SINKABLE2:%.*]] = add i32 [[V1]], [[V2]]813; CHECK-NEXT: indirectbr ptr [[INDIRECT_GOTO_DEST]], [label [[L1:%.*]], label %exit]814; CHECK: L1:815; CHECK-NEXT: indirectbr ptr [[INDIRECT_GOTO_DEST2]], [label [[L0]], label %exit]816; CHECK: exit:817; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SINKABLE]], [[L0]] ], [ [[SINKABLE2]], [[L1]] ]818; CHECK-NEXT: ret i32 [[R]]819;820entry:821 br label %L0822L0:823 %indirect.goto.dest = select i1 %cond, ptr blockaddress(@test19, %exit), ptr %address824 %v2 = call i32 @getv()825 %sinkable = mul i32 %v1, %v2826 %sinkable2 = add i32 %v1, %v2827 indirectbr ptr %indirect.goto.dest, [label %L1, label %exit]828 829L1:830 %indirect.goto.dest2 = select i1 %cond2, ptr blockaddress(@test19, %exit), ptr %address831 indirectbr ptr %indirect.goto.dest2, [label %L0, label %exit]832 833exit:834 %r = phi i32 [%sinkable, %L0], [%sinkable2, %L1]835 ret i32 %r836}837 838 839; Do not sink through a non-trivially replacable PHI if splitting predecessors840; not allowed in SplitBlockPredecessors().841define void @test20(ptr %s, i1 %b, i32 %v1, i32 %v2) personality ptr @__CxxFrameHandler3 {842; CHECK-LABEL: @test20(843; CHECK-NEXT: entry:844; CHECK-NEXT: br label [[WHILE_COND:%.*]]845; CHECK: while.cond:846; CHECK-NEXT: [[V:%.*]] = call i32 @getv()847; CHECK-NEXT: [[SINKABLE:%.*]] = mul i32 [[V]], [[V2:%.*]]848; CHECK-NEXT: [[SINKABLE2:%.*]] = add i32 [[V]], [[V2]]849; CHECK-NEXT: br i1 [[B:%.*]], label [[TRY_CONT:%.*]], label [[WHILE_BODY:%.*]]850; CHECK: while.body:851; CHECK-NEXT: invoke void @may_throw()852; CHECK-NEXT: to label [[WHILE_BODY2:%.*]] unwind label [[CATCH_DISPATCH:%.*]]853; CHECK: while.body2:854; CHECK-NEXT: invoke void @may_throw2()855; CHECK-NEXT: to label [[WHILE_COND]] unwind label [[CATCH_DISPATCH]]856; CHECK: catch.dispatch:857; CHECK-NEXT: [[DOTLCSSA1:%.*]] = phi i32 [ [[SINKABLE]], [[WHILE_BODY]] ], [ [[SINKABLE2]], [[WHILE_BODY2]] ]858; CHECK-NEXT: [[CP:%.*]] = cleanuppad within none []859; CHECK-NEXT: store i32 [[DOTLCSSA1]], ptr [[S:%.*]], align 4860; CHECK-NEXT: cleanupret from [[CP]] unwind to caller861; CHECK: try.cont:862; CHECK-NEXT: ret void863;864entry:865 br label %while.cond866while.cond:867 %v = call i32 @getv()868 %sinkable = mul i32 %v, %v2869 %sinkable2 = add i32 %v, %v2870 br i1 %b, label %try.cont, label %while.body871while.body:872 invoke void @may_throw()873 to label %while.body2 unwind label %catch.dispatch874while.body2:875 invoke void @may_throw2()876 to label %while.cond unwind label %catch.dispatch877catch.dispatch:878 %.lcssa1 = phi i32 [ %sinkable, %while.body ], [ %sinkable2, %while.body2 ]879 %cp = cleanuppad within none []880 store i32 %.lcssa1, ptr %s881 cleanupret from %cp unwind to caller882try.cont:883 ret void884}885 886; The sinkable call should be sunk into an exit block split. After splitting887; the exit block, BlockColor for new blocks should be added properly so888; that we should be able to access valid ColorVector.889define i32 @test21_pr36184(ptr %P, i1 %arg) personality ptr @__CxxFrameHandler3 {890; CHECK-LABEL: @test21_pr36184(891; CHECK-NEXT: entry:892; CHECK-NEXT: br label [[LOOP_PH:%.*]]893; CHECK: loop.ph:894; CHECK-NEXT: br label [[LOOP:%.*]]895; CHECK: Loop:896; CHECK-NEXT: br i1 [[ARG:%.*]], label [[CONTLOOP:%.*]], label [[OUT_SPLIT_LOOP_EXIT1:%.*]]897; CHECK: ContLoop:898; CHECK-NEXT: br i1 [[ARG]], label [[LOOP]], label [[OUT_SPLIT_LOOP_EXIT:%.*]]899; CHECK: Out.split.loop.exit:900; CHECK-NEXT: [[IDX_PH:%.*]] = phi i32 [ 0, [[CONTLOOP]] ]901; CHECK-NEXT: br label [[OUT:%.*]]902; CHECK: Out.split.loop.exit1:903; CHECK-NEXT: [[SINKABLECALL_LE:%.*]] = call i32 @strlen(ptr [[P:%.*]]) #[[ATTR3]]904; CHECK-NEXT: br label [[OUT]]905; CHECK: Out:906; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_PH]], [[OUT_SPLIT_LOOP_EXIT]] ], [ [[SINKABLECALL_LE]], [[OUT_SPLIT_LOOP_EXIT1]] ]907; CHECK-NEXT: ret i32 [[IDX]]908;909entry:910 br label %loop.ph911 912loop.ph:913 br label %Loop914 915Loop:916 %sinkableCall = call i32 @strlen( ptr %P ) readonly917 br i1 %arg, label %ContLoop, label %Out918 919ContLoop:920 br i1 %arg, label %Loop, label %Out921 922Out:923 %idx = phi i32 [ %sinkableCall, %Loop ], [0, %ContLoop ]924 ret i32 %idx925}926 927; We do not support splitting a landingpad block if BlockColors is not empty.928define void @test22(i1 %b, i32 %v1, i32 %v2) personality ptr @__CxxFrameHandler3 {929; CHECK-LABEL: @test22(930; CHECK-NEXT: entry:931; CHECK-NEXT: br label [[WHILE_COND:%.*]]932; CHECK: while.cond:933; CHECK-NEXT: br i1 [[B:%.*]], label [[TRY_CONT:%.*]], label [[WHILE_BODY:%.*]]934; CHECK: while.body:935; CHECK-NEXT: invoke void @may_throw()936; CHECK-NEXT: to label [[WHILE_BODY2:%.*]] unwind label [[LPADBB:%.*]]937; CHECK: while.body2:938; CHECK-NEXT: [[V:%.*]] = call i32 @getv()939; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[V]], [[V2:%.*]]940; CHECK-NEXT: invoke void @may_throw2()941; CHECK-NEXT: to label [[WHILE_COND]] unwind label [[LPADBB]]942; CHECK: lpadBB:943; CHECK-NEXT: [[DOTLCSSA1:%.*]] = phi i32 [ 0, [[WHILE_BODY]] ], [ [[MUL]], [[WHILE_BODY2]] ]944; CHECK-NEXT: [[TMP0:%.*]] = landingpad { ptr, i32 }945; CHECK-NEXT: catch ptr null946; CHECK-NEXT: br label [[LPADBBSUCC1:%.*]]947; CHECK: lpadBBSucc1:948; CHECK-NEXT: ret void949; CHECK: try.cont:950; CHECK-NEXT: ret void951;952entry:953 br label %while.cond954while.cond:955 br i1 %b, label %try.cont, label %while.body956 957while.body:958 invoke void @may_throw()959 to label %while.body2 unwind label %lpadBB960 961while.body2:962 %v = call i32 @getv()963 %mul = mul i32 %v, %v2964 invoke void @may_throw2()965 to label %while.cond unwind label %lpadBB966lpadBB:967 %.lcssa1 = phi i32 [ 0, %while.body ], [ %mul, %while.body2 ]968 landingpad { ptr, i32 }969 catch ptr null970 br label %lpadBBSucc1971 972lpadBBSucc1:973 ret void974 975try.cont:976 ret void977}978 979define i32 @not_willreturn(ptr %p) {980; CHECK-LABEL: @not_willreturn(981; CHECK-NEXT: [[X:%.*]] = call i32 @getv() #[[ATTR5:[0-9]+]]982; CHECK-NEXT: br label [[LOOP:%.*]]983; CHECK: loop:984; CHECK-NEXT: store volatile i8 0, ptr [[P:%.*]], align 1985; CHECK-NEXT: br i1 true, label [[LOOP]], label [[OUT:%.*]]986; CHECK: out:987; CHECK-NEXT: [[X_LCSSA:%.*]] = phi i32 [ [[X]], [[LOOP]] ]988; CHECK-NEXT: ret i32 [[X_LCSSA]]989;990 br label %loop991 992loop:993 %x = call i32 @getv() nounwind readnone994 store volatile i8 0, ptr %p995 br i1 true, label %loop, label %out996 997out:998 ret i32 %x999}1000 1001declare void @use.i32(i32)1002declare void @use.i64(i64)1003 1004; Don't duplicate freeze just because it's free.1005define i32 @duplicate_freeze(i1 %c, i32 %x) {1006; CHECK-LABEL: @duplicate_freeze(1007; CHECK-NEXT: entry:1008; CHECK-NEXT: [[FR:%.*]] = freeze i32 [[X:%.*]]1009; CHECK-NEXT: br label [[LOOP:%.*]]1010; CHECK: loop:1011; CHECK-NEXT: call void @use.i32(i32 [[FR]])1012; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[EXIT:%.*]]1013; CHECK: exit:1014; CHECK-NEXT: [[FR_LCSSA:%.*]] = phi i32 [ [[FR]], [[LOOP]] ]1015; CHECK-NEXT: ret i32 [[FR_LCSSA]]1016;1017entry:1018 br label %loop1019 1020loop:1021 %fr = freeze i32 %x1022 call void @use.i32(i32 %fr)1023 br i1 %c, label %loop, label %exit1024 1025exit:1026 ret i32 %fr1027}1028 1029; Don't duplicate ptrtoint just because it's free.1030define i64 @duplicate_ptrtoint(i1 %c, ptr %p) {1031; CHECK-LABEL: @duplicate_ptrtoint(1032; CHECK-NEXT: entry:1033; CHECK-NEXT: [[PI:%.*]] = ptrtoint ptr [[P:%.*]] to i641034; CHECK-NEXT: br label [[LOOP:%.*]]1035; CHECK: loop:1036; CHECK-NEXT: call void @use.i64(i64 [[PI]])1037; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[EXIT:%.*]]1038; CHECK: exit:1039; CHECK-NEXT: [[PI_LCSSA:%.*]] = phi i64 [ [[PI]], [[LOOP]] ]1040; CHECK-NEXT: ret i64 [[PI_LCSSA]]1041;1042entry:1043 br label %loop1044 1045loop:1046 %pi = ptrtoint ptr %p to i641047 call void @use.i64(i64 %pi)1048 br i1 %c, label %loop, label %exit1049 1050exit:1051 ret i64 %pi1052}1053 1054declare void @may_throw()1055declare void @may_throw2()1056declare i32 @__CxxFrameHandler3(...)1057declare i32 @getv()1058declare i1 @getc()1059declare void @f(ptr)1060declare void @g()1061