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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S -passes='loop-mssa(licm)' -verify-memoryssa %s | FileCheck %s3 4define i32 @reduce_umax(<2 x i32> %inv, i1 %c) {5; CHECK-LABEL: define i32 @reduce_umax(6; CHECK-SAME: <2 x i32> [[INV:%.*]], i1 [[C:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[REDUCE_UMAX:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[INV]])9; CHECK-NEXT: br label %[[LOOP:.*]]10; CHECK: [[LOOP]]:11; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]12; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 113; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[REDUCE_UMAX]]14; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false15; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]]16; CHECK: [[EXIT]]:17; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ]18; CHECK-NEXT: ret i32 [[IV_LCSSA]]19;20entry:21 br label %loop22 23loop:24 %iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]25 %iv.next = add i32 %iv, 126 br i1 %c, label %cond.true, label %exit27 28cond.true:29 %reduce.umax = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %inv)30 %backedge.cond = icmp ult i32 %iv, %reduce.umax31 br i1 %backedge.cond, label %loop, label %exit32 33exit:34 ret i32 %iv35}36 37define i32 @vp_umax(<2 x i32> %inv.l, <2 x i32> %inv.r, i1 %c) {38; CHECK-LABEL: define i32 @vp_umax(39; CHECK-SAME: <2 x i32> [[INV_L:%.*]], <2 x i32> [[INV_R:%.*]], i1 [[C:%.*]]) {40; CHECK-NEXT: [[ENTRY:.*]]:41; CHECK-NEXT: [[VP_UMAX:%.*]] = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> [[INV_L]], <2 x i32> [[INV_R]], <2 x i1> splat (i1 true), i32 2)42; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UMAX]], i32 043; CHECK-NEXT: br label %[[LOOP:.*]]44; CHECK: [[LOOP]]:45; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]46; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 147; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]48; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false49; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]]50; CHECK: [[EXIT]]:51; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ]52; CHECK-NEXT: ret i32 [[IV_LCSSA]]53;54entry:55 br label %loop56 57loop:58 %iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]59 %iv.next = add i32 %iv, 160 br i1 %c, label %cond.true, label %exit61 62cond.true:63 %vp.umax = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %inv.l, <2 x i32> %inv.r, <2 x i1> splat (i1 1), i32 2)64 %extract = extractelement <2 x i32> %vp.umax, i32 065 %backedge.cond = icmp ult i32 %iv, %extract66 br i1 %backedge.cond, label %loop, label %exit67 68exit:69 ret i32 %iv70}71 72define i32 @vp_udiv(<2 x i32> %inv.q, <2 x i32> %inv.d, i1 %c) {73; CHECK-LABEL: define i32 @vp_udiv(74; CHECK-SAME: <2 x i32> [[INV_Q:%.*]], <2 x i32> [[INV_D:%.*]], i1 [[C:%.*]]) {75; CHECK-NEXT: [[ENTRY:.*]]:76; CHECK-NEXT: br label %[[LOOP:.*]]77; CHECK: [[LOOP]]:78; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]79; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 180; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]81; CHECK: [[COND_TRUE]]:82; CHECK-NEXT: [[VP_UDIV:%.*]] = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> [[INV_Q]], <2 x i32> [[INV_D]], <2 x i1> splat (i1 true), i32 2)83; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UDIV]], i32 084; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]85; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]]86; CHECK: [[EXIT]]:87; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]88; CHECK-NEXT: ret i32 [[IV_LCSSA]]89;90entry:91 br label %loop92 93loop:94 %iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]95 %iv.next = add i32 %iv, 196 br i1 %c, label %cond.true, label %exit97 98cond.true:99 %vp.udiv = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %inv.q, <2 x i32> %inv.d, <2 x i1> splat (i1 1), i32 2)100 %extract = extractelement <2 x i32> %vp.udiv, i32 0101 %backedge.cond = icmp ult i32 %iv, %extract102 br i1 %backedge.cond, label %loop, label %exit103 104exit:105 ret i32 %iv106}107 108define i32 @vp_load(ptr %inv, i1 %c) {109; CHECK-LABEL: define i32 @vp_load(110; CHECK-SAME: ptr [[INV:%.*]], i1 [[C:%.*]]) {111; CHECK-NEXT: [[ENTRY:.*]]:112; CHECK-NEXT: br label %[[LOOP:.*]]113; CHECK: [[LOOP]]:114; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]115; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1116; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]117; CHECK: [[COND_TRUE]]:118; CHECK-NEXT: [[VP_LOAD:%.*]] = call <2 x i32> @llvm.vp.load.v2i32.p0(ptr [[INV]], <2 x i1> splat (i1 true), i32 2)119; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_LOAD]], i32 0120; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]121; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]]122; CHECK: [[EXIT]]:123; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]124; CHECK-NEXT: ret i32 [[IV_LCSSA]]125;126entry:127 br label %loop128 129loop:130 %iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]131 %iv.next = add i32 %iv, 1132 br i1 %c, label %cond.true, label %exit133 134cond.true:135 %vp.load = call <2 x i32> @llvm.vp.load.v2i32(ptr %inv, <2 x i1> splat (i1 1), i32 2)136 %extract = extractelement <2 x i32> %vp.load, i32 0137 %backedge.cond = icmp ult i32 %iv, %extract138 br i1 %backedge.cond, label %loop, label %exit139 140exit:141 ret i32 %iv142}143 144define i32 @vp_store(<2 x i32> %inv.v, ptr %inv.p, i1 %c) {145; CHECK-LABEL: define i32 @vp_store(146; CHECK-SAME: <2 x i32> [[INV_V:%.*]], ptr [[INV_P:%.*]], i1 [[C:%.*]]) {147; CHECK-NEXT: [[ENTRY:.*]]:148; CHECK-NEXT: br label %[[LOOP:.*]]149; CHECK: [[LOOP]]:150; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]151; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1152; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]153; CHECK: [[COND_TRUE]]:154; CHECK-NEXT: call void @llvm.vp.store.v2i32.p0(<2 x i32> [[INV_V]], ptr [[INV_P]], <2 x i1> splat (i1 true), i32 2)155; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], 10156; CHECK-NEXT: br i1 [[BACKEDGE_COND]], label %[[LOOP]], label %[[EXIT]]157; CHECK: [[EXIT]]:158; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]159; CHECK-NEXT: ret i32 [[IV_LCSSA]]160;161entry:162 br label %loop163 164loop:165 %iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]166 %iv.next = add i32 %iv, 1167 br i1 %c, label %cond.true, label %exit168 169cond.true:170 call void @llvm.vp.store.v2i32(<2 x i32> %inv.v, ptr %inv.p, <2 x i1> splat (i1 1), i32 2)171 %backedge.cond = icmp ult i32 %iv, 10172 br i1 %backedge.cond, label %loop, label %exit173 174exit:175 ret i32 %iv176}177