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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=load-store-vectorizer --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s3; RUN: opt -S -passes=load-store-vectorizer --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s4; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s5; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s6 7target triple = "amdgcn--"8 9define amdgpu_kernel void @load_unknown_offset_align1_i8(ptr addrspace(1) noalias %out, i32 %offset) #0 {10; ALIGNED-LABEL: @load_unknown_offset_align1_i8(11; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 1, addrspace(5)12; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]13; ALIGNED-NEXT: [[VAL0:%.*]] = load i8, ptr addrspace(5) [[PTR0]], align 114; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[PTR0]], i32 115; ALIGNED-NEXT: [[VAL1:%.*]] = load i8, ptr addrspace(5) [[PTR1]], align 116; ALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL0]], [[VAL1]]17; ALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 118; ALIGNED-NEXT: ret void19;20; UNALIGNED-LABEL: @load_unknown_offset_align1_i8(21; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 1, addrspace(5)22; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]23; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr addrspace(5) [[PTR0]], align 124; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i32 025; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i32 126; UNALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL01]], [[VAL12]]27; UNALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 128; UNALIGNED-NEXT: ret void29;30 %alloca = alloca [128 x i8], align 1, addrspace(5)31 %ptr0 = getelementptr inbounds [128 x i8], ptr addrspace(5) %alloca, i32 0, i32 %offset32 %val0 = load i8, ptr addrspace(5) %ptr0, align 133 %ptr1 = getelementptr inbounds i8, ptr addrspace(5) %ptr0, i32 134 %val1 = load i8, ptr addrspace(5) %ptr1, align 135 %add = add i8 %val0, %val136 store i8 %add, ptr addrspace(1) %out37 ret void38}39 40define amdgpu_kernel void @load_unknown_offset_align1_i16(ptr addrspace(1) noalias %out, i32 %offset) #0 {41; ALIGNED-LABEL: @load_unknown_offset_align1_i16(42; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i16], align 1, addrspace(5)43; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i16], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]44; ALIGNED-NEXT: [[VAL0:%.*]] = load i16, ptr addrspace(5) [[PTR0]], align 145; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i16, ptr addrspace(5) [[PTR0]], i32 146; ALIGNED-NEXT: [[VAL1:%.*]] = load i16, ptr addrspace(5) [[PTR1]], align 147; ALIGNED-NEXT: [[ADD:%.*]] = add i16 [[VAL0]], [[VAL1]]48; ALIGNED-NEXT: store i16 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 249; ALIGNED-NEXT: ret void50;51; UNALIGNED-LABEL: @load_unknown_offset_align1_i16(52; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i16], align 1, addrspace(5)53; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i16], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]54; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[PTR0]], align 155; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 056; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 157; UNALIGNED-NEXT: [[ADD:%.*]] = add i16 [[VAL01]], [[VAL12]]58; UNALIGNED-NEXT: store i16 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 259; UNALIGNED-NEXT: ret void60;61 %alloca = alloca [128 x i16], align 1, addrspace(5)62 %ptr0 = getelementptr inbounds [128 x i16], ptr addrspace(5) %alloca, i32 0, i32 %offset63 %val0 = load i16, ptr addrspace(5) %ptr0, align 164 %ptr1 = getelementptr inbounds i16, ptr addrspace(5) %ptr0, i32 165 %val1 = load i16, ptr addrspace(5) %ptr1, align 166 %add = add i16 %val0, %val167 store i16 %add, ptr addrspace(1) %out68 ret void69}70 71; FIXME: Although the offset is unknown here, we know it is a multiple72; of the element size, so should still be align 473define amdgpu_kernel void @load_unknown_offset_align1_i32(ptr addrspace(1) noalias %out, i32 %offset) #0 {74; ALIGNED-LABEL: @load_unknown_offset_align1_i32(75; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 1, addrspace(5)76; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]77; ALIGNED-NEXT: [[VAL0:%.*]] = load i32, ptr addrspace(5) [[PTR0]], align 178; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i32, ptr addrspace(5) [[PTR0]], i32 179; ALIGNED-NEXT: [[VAL1:%.*]] = load i32, ptr addrspace(5) [[PTR1]], align 180; ALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL0]], [[VAL1]]81; ALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 482; ALIGNED-NEXT: ret void83;84; UNALIGNED-LABEL: @load_unknown_offset_align1_i32(85; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 1, addrspace(5)86; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]87; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(5) [[PTR0]], align 188; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 089; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 190; UNALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL01]], [[VAL12]]91; UNALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 492; UNALIGNED-NEXT: ret void93;94 %alloca = alloca [128 x i32], align 1, addrspace(5)95 %ptr0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca, i32 0, i32 %offset96 %val0 = load i32, ptr addrspace(5) %ptr0, align 197 %ptr1 = getelementptr inbounds i32, ptr addrspace(5) %ptr0, i32 198 %val1 = load i32, ptr addrspace(5) %ptr1, align 199 %add = add i32 %val0, %val1100 store i32 %add, ptr addrspace(1) %out101 ret void102}103 104; Make sure alloca alignment isn't decreased105define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(ptr addrspace(1) noalias %out, i32 %offset) #0 {106; ALIGNED-LABEL: @load_alloca16_unknown_offset_align1_i32(107; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 16, addrspace(5)108; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]109; ALIGNED-NEXT: [[VAL0:%.*]] = load i32, ptr addrspace(5) [[PTR0]], align 1110; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i32, ptr addrspace(5) [[PTR0]], i32 1111; ALIGNED-NEXT: [[VAL1:%.*]] = load i32, ptr addrspace(5) [[PTR1]], align 1112; ALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL0]], [[VAL1]]113; ALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4114; ALIGNED-NEXT: ret void115;116; UNALIGNED-LABEL: @load_alloca16_unknown_offset_align1_i32(117; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 16, addrspace(5)118; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]119; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(5) [[PTR0]], align 4120; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0121; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1122; UNALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL01]], [[VAL12]]123; UNALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4124; UNALIGNED-NEXT: ret void125;126 %alloca = alloca [128 x i32], align 16, addrspace(5)127 %ptr0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca, i32 0, i32 %offset128 %val0 = load i32, ptr addrspace(5) %ptr0, align 1129 %ptr1 = getelementptr inbounds i32, ptr addrspace(5) %ptr0, i32 1130 %val1 = load i32, ptr addrspace(5) %ptr1, align 1131 %add = add i32 %val0, %val1132 store i32 %add, ptr addrspace(1) %out133 ret void134}135 136define amdgpu_kernel void @store_unknown_offset_align1_i8(ptr addrspace(1) noalias %out, i32 %offset) #0 {137; ALIGNED-LABEL: @store_unknown_offset_align1_i8(138; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 1, addrspace(5)139; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]140; ALIGNED-NEXT: store i8 9, ptr addrspace(5) [[PTR0]], align 1141; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[PTR0]], i32 1142; ALIGNED-NEXT: store i8 10, ptr addrspace(5) [[PTR1]], align 1143; ALIGNED-NEXT: ret void144;145; UNALIGNED-LABEL: @store_unknown_offset_align1_i8(146; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 1, addrspace(5)147; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]148; UNALIGNED-NEXT: store <2 x i8> <i8 9, i8 10>, ptr addrspace(5) [[PTR0]], align 1149; UNALIGNED-NEXT: ret void150;151 %alloca = alloca [128 x i8], align 1, addrspace(5)152 %ptr0 = getelementptr inbounds [128 x i8], ptr addrspace(5) %alloca, i32 0, i32 %offset153 store i8 9, ptr addrspace(5) %ptr0, align 1154 %ptr1 = getelementptr inbounds i8, ptr addrspace(5) %ptr0, i32 1155 store i8 10, ptr addrspace(5) %ptr1, align 1156 ret void157}158 159define amdgpu_kernel void @store_unknown_offset_align1_i16(ptr addrspace(1) noalias %out, i32 %offset) #0 {160; ALIGNED-LABEL: @store_unknown_offset_align1_i16(161; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i16], align 1, addrspace(5)162; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i16], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]163; ALIGNED-NEXT: store i16 9, ptr addrspace(5) [[PTR0]], align 1164; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i16, ptr addrspace(5) [[PTR0]], i32 1165; ALIGNED-NEXT: store i16 10, ptr addrspace(5) [[PTR1]], align 1166; ALIGNED-NEXT: ret void167;168; UNALIGNED-LABEL: @store_unknown_offset_align1_i16(169; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i16], align 1, addrspace(5)170; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i16], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]171; UNALIGNED-NEXT: store <2 x i16> <i16 9, i16 10>, ptr addrspace(5) [[PTR0]], align 1172; UNALIGNED-NEXT: ret void173;174 %alloca = alloca [128 x i16], align 1, addrspace(5)175 %ptr0 = getelementptr inbounds [128 x i16], ptr addrspace(5) %alloca, i32 0, i32 %offset176 store i16 9, ptr addrspace(5) %ptr0, align 1177 %ptr1 = getelementptr inbounds i16, ptr addrspace(5) %ptr0, i32 1178 store i16 10, ptr addrspace(5) %ptr1, align 1179 ret void180}181 182; FIXME: Although the offset is unknown here, we know it is a multiple183; of the element size, so it still should be align 4.184 185define amdgpu_kernel void @store_unknown_offset_align1_i32(ptr addrspace(1) noalias %out, i32 %offset) #0 {186; ALIGNED-LABEL: @store_unknown_offset_align1_i32(187; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 1, addrspace(5)188; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]189; ALIGNED-NEXT: store i32 9, ptr addrspace(5) [[PTR0]], align 1190; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i32, ptr addrspace(5) [[PTR0]], i32 1191; ALIGNED-NEXT: store i32 10, ptr addrspace(5) [[PTR1]], align 1192; ALIGNED-NEXT: ret void193;194; UNALIGNED-LABEL: @store_unknown_offset_align1_i32(195; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 1, addrspace(5)196; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]197; UNALIGNED-NEXT: store <2 x i32> <i32 9, i32 10>, ptr addrspace(5) [[PTR0]], align 1198; UNALIGNED-NEXT: ret void199;200 %alloca = alloca [128 x i32], align 1, addrspace(5)201 %ptr0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca, i32 0, i32 %offset202 store i32 9, ptr addrspace(5) %ptr0, align 1203 %ptr1 = getelementptr inbounds i32, ptr addrspace(5) %ptr0, i32 1204 store i32 10, ptr addrspace(5) %ptr1, align 1205 ret void206}207 208define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32() {209; CHECK-LABEL: @merge_private_store_4_vector_elts_loads_v4i32(210; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i32], align 4, addrspace(5)211; CHECK-NEXT: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, ptr addrspace(5) [[ALLOCA]], align 4212; CHECK-NEXT: ret void213;214 %alloca = alloca [8 x i32], align 1, addrspace(5)215 %out.gep.1 = getelementptr i32, ptr addrspace(5) %alloca, i32 1216 %out.gep.2 = getelementptr i32, ptr addrspace(5) %alloca, i32 2217 %out.gep.3 = getelementptr i32, ptr addrspace(5) %alloca, i32 3218 219 store i32 9, ptr addrspace(5) %alloca, align 1220 store i32 1, ptr addrspace(5) %out.gep.1, align 1221 store i32 23, ptr addrspace(5) %out.gep.2, align 1222 store i32 19, ptr addrspace(5) %out.gep.3, align 1223 ret void224}225 226define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8() {227; CHECK-LABEL: @merge_private_store_4_vector_elts_loads_v4i8(228; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i8], align 4, addrspace(5)229; CHECK-NEXT: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, ptr addrspace(5) [[ALLOCA]], align 4230; CHECK-NEXT: ret void231;232 %alloca = alloca [8 x i8], align 1, addrspace(5)233 %out.gep.1 = getelementptr i8, ptr addrspace(5) %alloca, i8 1234 %out.gep.2 = getelementptr i8, ptr addrspace(5) %alloca, i8 2235 %out.gep.3 = getelementptr i8, ptr addrspace(5) %alloca, i8 3236 237 store i8 9, ptr addrspace(5) %alloca, align 1238 store i8 1, ptr addrspace(5) %out.gep.1, align 1239 store i8 23, ptr addrspace(5) %out.gep.2, align 1240 store i8 19, ptr addrspace(5) %out.gep.3, align 1241 ret void242}243 244define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i32() {245; CHECK-LABEL: @merge_private_load_4_vector_elts_loads_v4i32(246; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i32], align 4, addrspace(5)247; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(5) [[ALLOCA]], align 4248; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0249; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1250; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2251; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3252; CHECK-NEXT: ret void253;254 %alloca = alloca [8 x i32], align 1, addrspace(5)255 %out.gep.1 = getelementptr i32, ptr addrspace(5) %alloca, i32 1256 %out.gep.2 = getelementptr i32, ptr addrspace(5) %alloca, i32 2257 %out.gep.3 = getelementptr i32, ptr addrspace(5) %alloca, i32 3258 259 %load0 = load i32, ptr addrspace(5) %alloca, align 1260 %load1 = load i32, ptr addrspace(5) %out.gep.1, align 1261 %load2 = load i32, ptr addrspace(5) %out.gep.2, align 1262 %load3 = load i32, ptr addrspace(5) %out.gep.3, align 1263 ret void264}265 266define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i8() {267; CHECK-LABEL: @merge_private_load_4_vector_elts_loads_v4i8(268; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i8], align 4, addrspace(5)269; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(5) [[ALLOCA]], align 4270; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0271; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1272; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2273; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3274; CHECK-NEXT: ret void275;276 %alloca = alloca [8 x i8], align 1, addrspace(5)277 %out.gep.1 = getelementptr i8, ptr addrspace(5) %alloca, i8 1278 %out.gep.2 = getelementptr i8, ptr addrspace(5) %alloca, i8 2279 %out.gep.3 = getelementptr i8, ptr addrspace(5) %alloca, i8 3280 281 %load0 = load i8, ptr addrspace(5) %alloca, align 1282 %load1 = load i8, ptr addrspace(5) %out.gep.1, align 1283 %load2 = load i8, ptr addrspace(5) %out.gep.2, align 1284 %load3 = load i8, ptr addrspace(5) %out.gep.3, align 1285 ret void286}287 288; Make sure we don't think the alignment will increase if the base address isn't an alloca289define void @private_store_2xi16_align2_not_alloca(ptr addrspace(5) %p, ptr addrspace(5) %r) #0 {290; ALIGNED-LABEL: @private_store_2xi16_align2_not_alloca(291; ALIGNED-NEXT: [[GEP_R:%.*]] = getelementptr i16, ptr addrspace(5) [[R:%.*]], i32 1292; ALIGNED-NEXT: store i16 1, ptr addrspace(5) [[R]], align 2293; ALIGNED-NEXT: store i16 2, ptr addrspace(5) [[GEP_R]], align 2294; ALIGNED-NEXT: ret void295;296; UNALIGNED-LABEL: @private_store_2xi16_align2_not_alloca(297; UNALIGNED-NEXT: store <2 x i16> <i16 1, i16 2>, ptr addrspace(5) [[R:%.*]], align 2298; UNALIGNED-NEXT: ret void299;300 %gep.r = getelementptr i16, ptr addrspace(5) %r, i32 1301 store i16 1, ptr addrspace(5) %r, align 2302 store i16 2, ptr addrspace(5) %gep.r, align 2303 ret void304}305 306define void @private_store_2xi16_align1_not_alloca(ptr addrspace(5) %p, ptr addrspace(5) %r) #0 {307; ALIGNED-LABEL: @private_store_2xi16_align1_not_alloca(308; ALIGNED-NEXT: [[GEP_R:%.*]] = getelementptr i16, ptr addrspace(5) [[R:%.*]], i32 1309; ALIGNED-NEXT: store i16 1, ptr addrspace(5) [[R]], align 1310; ALIGNED-NEXT: store i16 2, ptr addrspace(5) [[GEP_R]], align 1311; ALIGNED-NEXT: ret void312;313; UNALIGNED-LABEL: @private_store_2xi16_align1_not_alloca(314; UNALIGNED-NEXT: store <2 x i16> <i16 1, i16 2>, ptr addrspace(5) [[R:%.*]], align 1315; UNALIGNED-NEXT: ret void316;317 %gep.r = getelementptr i16, ptr addrspace(5) %r, i32 1318 store i16 1, ptr addrspace(5) %r, align 1319 store i16 2, ptr addrspace(5) %gep.r, align 1320 ret void321}322 323define i32 @private_load_2xi16_align2_not_alloca(ptr addrspace(5) %p) #0 {324; ALIGNED-LABEL: @private_load_2xi16_align2_not_alloca(325; ALIGNED-NEXT: [[GEP_P:%.*]] = getelementptr i16, ptr addrspace(5) [[P:%.*]], i64 1326; ALIGNED-NEXT: [[P_0:%.*]] = load i16, ptr addrspace(5) [[P]], align 2327; ALIGNED-NEXT: [[P_1:%.*]] = load i16, ptr addrspace(5) [[GEP_P]], align 2328; ALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_0]] to i32329; ALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_1]] to i32330; ALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16331; ALIGNED-NEXT: [[OR:%.*]] = or i32 [[ZEXT_0]], [[SHL_1]]332; ALIGNED-NEXT: ret i32 [[OR]]333;334; UNALIGNED-LABEL: @private_load_2xi16_align2_not_alloca(335; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[P:%.*]], align 2336; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0337; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1338; UNALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_01]] to i32339; UNALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_12]] to i32340; UNALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16341; UNALIGNED-NEXT: [[OR:%.*]] = or i32 [[ZEXT_0]], [[SHL_1]]342; UNALIGNED-NEXT: ret i32 [[OR]]343;344 %gep.p = getelementptr i16, ptr addrspace(5) %p, i64 1345 %p.0 = load i16, ptr addrspace(5) %p, align 2346 %p.1 = load i16, ptr addrspace(5) %gep.p, align 2347 %zext.0 = zext i16 %p.0 to i32348 %zext.1 = zext i16 %p.1 to i32349 %shl.1 = shl i32 %zext.1, 16350 %or = or i32 %zext.0, %shl.1351 ret i32 %or352}353 354define i32 @private_load_2xi16_align1_not_alloca(ptr addrspace(5) %p) #0 {355; ALIGNED-LABEL: @private_load_2xi16_align1_not_alloca(356; ALIGNED-NEXT: [[GEP_P:%.*]] = getelementptr i16, ptr addrspace(5) [[P:%.*]], i64 1357; ALIGNED-NEXT: [[P_0:%.*]] = load i16, ptr addrspace(5) [[P]], align 1358; ALIGNED-NEXT: [[P_1:%.*]] = load i16, ptr addrspace(5) [[GEP_P]], align 1359; ALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_0]] to i32360; ALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_1]] to i32361; ALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16362; ALIGNED-NEXT: [[OR:%.*]] = or i32 [[ZEXT_0]], [[SHL_1]]363; ALIGNED-NEXT: ret i32 [[OR]]364;365; UNALIGNED-LABEL: @private_load_2xi16_align1_not_alloca(366; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[P:%.*]], align 1367; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0368; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1369; UNALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_01]] to i32370; UNALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_12]] to i32371; UNALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16372; UNALIGNED-NEXT: [[OR:%.*]] = or i32 [[ZEXT_0]], [[SHL_1]]373; UNALIGNED-NEXT: ret i32 [[OR]]374;375 %gep.p = getelementptr i16, ptr addrspace(5) %p, i64 1376 %p.0 = load i16, ptr addrspace(5) %p, align 1377 %p.1 = load i16, ptr addrspace(5) %gep.p, align 1378 %zext.0 = zext i16 %p.0 to i32379 %zext.1 = zext i16 %p.1 to i32380 %shl.1 = shl i32 %zext.1, 16381 %or = or i32 %zext.0, %shl.1382 ret i32 %or383}384 385define void @load_alloca16_unknown_offset_align1_i8(ptr addrspace(1) noalias %out, i32 %offset) #0 {386; ALIGNED-LABEL: @load_alloca16_unknown_offset_align1_i8(387; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 16, addrspace(5)388; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]389; ALIGNED-NEXT: [[VAL0:%.*]] = load i8, ptr addrspace(5) [[PTR0]], align 1390; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[PTR0]], i32 1391; ALIGNED-NEXT: [[VAL1:%.*]] = load i8, ptr addrspace(5) [[PTR1]], align 1392; ALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL0]], [[VAL1]]393; ALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 1394; ALIGNED-NEXT: ret void395;396; UNALIGNED-LABEL: @load_alloca16_unknown_offset_align1_i8(397; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 16, addrspace(5)398; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]399; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr addrspace(5) [[PTR0]], align 1400; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0401; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1402; UNALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL01]], [[VAL12]]403; UNALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 1404; UNALIGNED-NEXT: ret void405;406 %alloca = alloca [128 x i8], align 16, addrspace(5)407 %ptr0 = getelementptr inbounds [128 x i8], ptr addrspace(5) %alloca, i32 0, i32 %offset408 %val0 = load i8, ptr addrspace(5) %ptr0, align 1409 %ptr1 = getelementptr inbounds i8, ptr addrspace(5) %ptr0, i32 1410 %val1 = load i8, ptr addrspace(5) %ptr1, align 1411 %add = add i8 %val0, %val1412 store i8 %add, ptr addrspace(1) %out413 ret void414}415 416define void @store_alloca16_unknown_offset_align1_i32(ptr addrspace(1) noalias %out, i32 %offset) #0 {417; ALIGNED-LABEL: @store_alloca16_unknown_offset_align1_i32(418; ALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 16, addrspace(5)419; ALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]420; ALIGNED-NEXT: store i32 9, ptr addrspace(5) [[PTR0]], align 1421; ALIGNED-NEXT: [[PTR1:%.*]] = getelementptr inbounds i32, ptr addrspace(5) [[PTR0]], i32 1422; ALIGNED-NEXT: store i32 10, ptr addrspace(5) [[PTR1]], align 1423; ALIGNED-NEXT: ret void424;425; UNALIGNED-LABEL: @store_alloca16_unknown_offset_align1_i32(426; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 16, addrspace(5)427; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]428; UNALIGNED-NEXT: store <2 x i32> <i32 9, i32 10>, ptr addrspace(5) [[PTR0]], align 4429; UNALIGNED-NEXT: ret void430;431 %alloca = alloca [128 x i32], align 16, addrspace(5)432 %ptr0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca, i32 0, i32 %offset433 store i32 9, ptr addrspace(5) %ptr0, align 1434 %ptr1 = getelementptr inbounds i32, ptr addrspace(5) %ptr0, i32 1435 store i32 10, ptr addrspace(5) %ptr1, align 1436 ret void437}438 439attributes #0 = { nounwind }440