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1; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s2; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s3 4declare i32 @llvm.amdgcn.workitem.id.x() #15 6; CHECK-LABEL: @basic_merge_sext_index(7; CHECK: sext i32 %id.x to i648; CHECK: load <2 x float>9; CHECK: store <2 x float> zeroinitializer10define amdgpu_kernel void @basic_merge_sext_index(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b, ptr addrspace(1) nocapture readonly %c) #0 {11entry:12 %id.x = call i32 @llvm.amdgcn.workitem.id.x()13 %sext.id.x = sext i32 %id.x to i6414 %a.idx.x = getelementptr inbounds float, ptr addrspace(1) %a, i64 %sext.id.x15 %c.idx.x = getelementptr inbounds float, ptr addrspace(1) %c, i64 %sext.id.x16 %a.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %a.idx.x, i64 117 %c.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %c.idx.x, i64 118 19 %ld.c = load float, ptr addrspace(1) %c.idx.x, align 420 %ld.c.idx.1 = load float, ptr addrspace(1) %c.idx.x.1, align 421 22 store float 0.0, ptr addrspace(1) %a.idx.x, align 423 store float 0.0, ptr addrspace(1) %a.idx.x.1, align 424 25 %add = fadd float %ld.c, %ld.c.idx.126 store float %add, ptr addrspace(1) %b, align 427 ret void28}29 30; CHECK-LABEL: @basic_merge_zext_index(31; CHECK: zext i32 %id.x to i6432; CHECK: load <2 x float>33; CHECK: store <2 x float>34define amdgpu_kernel void @basic_merge_zext_index(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b, ptr addrspace(1) nocapture readonly %c) #0 {35entry:36 %id.x = call i32 @llvm.amdgcn.workitem.id.x()37 %zext.id.x = zext i32 %id.x to i6438 %a.idx.x = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x39 %c.idx.x = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x40 %a.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %a.idx.x, i64 141 %c.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %c.idx.x, i64 142 43 %ld.c = load float, ptr addrspace(1) %c.idx.x, align 444 %ld.c.idx.1 = load float, ptr addrspace(1) %c.idx.x.1, align 445 store float 0.0, ptr addrspace(1) %a.idx.x, align 446 store float 0.0, ptr addrspace(1) %a.idx.x.1, align 447 48 %add = fadd float %ld.c, %ld.c.idx.149 store float %add, ptr addrspace(1) %b, align 450 ret void51}52 53; CHECK-LABEL: @merge_op_zext_index(54; CHECK: load <2 x float>55; CHECK: store <2 x float>56define amdgpu_kernel void @merge_op_zext_index(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c) #0 {57entry:58 %id.x = call i32 @llvm.amdgcn.workitem.id.x()59 %shl = shl i32 %id.x, 260 %zext.id.x = zext i32 %shl to i6461 %a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x62 %c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x63 64 %id.x.1 = or disjoint i32 %shl, 165 %id.x.1.ext = zext i32 %id.x.1 to i6466 67 %a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext68 %c.1 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %id.x.1.ext69 70 %ld.c.0 = load float, ptr addrspace(1) %c.0, align 471 store float 0.0, ptr addrspace(1) %a.0, align 472 %ld.c.1 = load float, ptr addrspace(1) %c.1, align 473 store float 0.0, ptr addrspace(1) %a.1, align 474 75 %add = fadd float %ld.c.0, %ld.c.176 store float %add, ptr addrspace(1) %b, align 477 ret void78}79 80; CHECK-LABEL: @merge_op_sext_index(81; CHECK: load <2 x float>82; CHECK: store <2 x float>83define amdgpu_kernel void @merge_op_sext_index(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c) #0 {84entry:85 %id.x = call i32 @llvm.amdgcn.workitem.id.x()86 %shl = shl i32 %id.x, 287 %zext.id.x = sext i32 %shl to i6488 %a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x89 %c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x90 91 %id.x.1 = or disjoint i32 %shl, 192 %id.x.1.ext = sext i32 %id.x.1 to i6493 94 %a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext95 %c.1 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %id.x.1.ext96 97 %ld.c.0 = load float, ptr addrspace(1) %c.0, align 498 store float 0.0, ptr addrspace(1) %a.0, align 499 %ld.c.1 = load float, ptr addrspace(1) %c.1, align 4100 store float 0.0, ptr addrspace(1) %a.1, align 4101 102 %add = fadd float %ld.c.0, %ld.c.1103 store float %add, ptr addrspace(1) %b, align 4104 ret void105}106 107; This case fails to vectorize if not using the extra extension108; handling in isConsecutiveAccess.109 110; CHECK-LABEL: @zext_trunc_phi_1(111; CHECK: loop:112; CHECK: load <2 x i32>113; CHECK: store <2 x i32>114define amdgpu_kernel void @zext_trunc_phi_1(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c, i32 %n, i64 %arst, i64 %aoeu) #0 {115entry:116 %cmp0 = icmp eq i32 %n, 0117 br i1 %cmp0, label %exit, label %loop118 119loop:120 %indvars.iv = phi i64 [ %indvars.iv.next, %loop ], [ 0, %entry ]121 %trunc.iv = trunc i64 %indvars.iv to i32122 %idx = shl i32 %trunc.iv, 4123 124 %idx.ext = zext i32 %idx to i64125 %c.0 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.ext126 %a.0 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.ext127 128 %idx.1 = or disjoint i32 %idx, 1129 %idx.1.ext = zext i32 %idx.1 to i64130 %c.1 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.1.ext131 %a.1 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.1.ext132 133 %ld.c.0 = load i32, ptr addrspace(1) %c.0, align 4134 store i32 %ld.c.0, ptr addrspace(1) %a.0, align 4135 %ld.c.1 = load i32, ptr addrspace(1) %c.1, align 4136 store i32 %ld.c.1, ptr addrspace(1) %a.1, align 4137 138 %indvars.iv.next = add i64 %indvars.iv, 1139 %lftr.wideiv = trunc i64 %indvars.iv.next to i32140 141 %exitcond = icmp eq i32 %lftr.wideiv, %n142 br i1 %exitcond, label %exit, label %loop143 144exit:145 ret void146}147 148attributes #0 = { nounwind }149attributes #1 = { nounwind readnone }150