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1; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-ALIGNED,ALIGNED,ALL %s2; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ALIGNED,ALL %s3; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ALIGNED,ALL %s4; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-UNALIGNED,UNALIGNED,ALL %s5; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-UNALIGNED,UNALIGNED,ALL %s6; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-UNALIGNED,UNALIGNED,ALL %s7 8; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i329; ELT4-ALIGNED: store i3210; ELT4-ALIGNED: store i3211; ELT4-ALIGNED: store i3212; ELT4-ALIGNED: store i3213 14; ELT8: store <2 x i32>15; ELT8: store <2 x i32>16 17; ELT16-UNALIGNED: store <4 x i32>18define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32(ptr addrspace(5) %out) #0 {19 %out.gep.1 = getelementptr i32, ptr addrspace(5) %out, i32 120 %out.gep.2 = getelementptr i32, ptr addrspace(5) %out, i32 221 %out.gep.3 = getelementptr i32, ptr addrspace(5) %out, i32 322 23 store i32 9, ptr addrspace(5) %out24 store i32 1, ptr addrspace(5) %out.gep.125 store i32 23, ptr addrspace(5) %out.gep.226 store i32 19, ptr addrspace(5) %out.gep.327 ret void28}29 30; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align1(31; ALIGNED: store i32 9, ptr addrspace(5) %out, align 132; ALIGNED: store i32 1, ptr addrspace(5) %out.gep.1, align 133; ALIGNED: store i32 23, ptr addrspace(5) %out.gep.2, align 134; ALIGNED: store i32 19, ptr addrspace(5) %out.gep.3, align 135 36; ELT16-UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, ptr addrspace(5) %out, align 137 38; ELT8-UNALIGNED: store <2 x i32> <i32 9, i32 1>, ptr addrspace(5) %out, align 139; ELT8-UNALIGNED: store <2 x i32> <i32 23, i32 19>, ptr addrspace(5) %out.gep.2, align 140 41; ELT4-UNALIGNED: store i3242; ELT4-UNALIGNED: store i3243; ELT4-UNALIGNED: store i3244; ELT4-UNALIGNED: store i3245define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align1(ptr addrspace(5) %out) #0 {46 %out.gep.1 = getelementptr i32, ptr addrspace(5) %out, i32 147 %out.gep.2 = getelementptr i32, ptr addrspace(5) %out, i32 248 %out.gep.3 = getelementptr i32, ptr addrspace(5) %out, i32 349 50 store i32 9, ptr addrspace(5) %out, align 151 store i32 1, ptr addrspace(5) %out.gep.1, align 152 store i32 23, ptr addrspace(5) %out.gep.2, align 153 store i32 19, ptr addrspace(5) %out.gep.3, align 154 ret void55}56 57; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align2(58; ALIGNED: store i3259; ALIGNED: store i3260; ALIGNED: store i3261; ALIGNED: store i3262; ELT4-UNALIGNED: store i3263; ELT4-UNALIGNED: store i3264; ELT4-UNALIGNED: store i3265; ELT4-UNALIGNED: store i3266; ELT8-UNALIGNED: store <2 x i32>67; ELT8-UNALIGNED: store <2 x i32>68; ELT16-UNALIGNED: store <4 x i32>69define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align2(ptr addrspace(5) %out) #0 {70 %out.gep.1 = getelementptr i32, ptr addrspace(5) %out, i32 171 %out.gep.2 = getelementptr i32, ptr addrspace(5) %out, i32 272 %out.gep.3 = getelementptr i32, ptr addrspace(5) %out, i32 373 74 store i32 9, ptr addrspace(5) %out, align 275 store i32 1, ptr addrspace(5) %out.gep.1, align 276 store i32 23, ptr addrspace(5) %out.gep.2, align 277 store i32 19, ptr addrspace(5) %out.gep.3, align 278 ret void79}80 81; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8(82; ALL: store <4 x i8>83define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8(ptr addrspace(5) %out) #0 {84 %out.gep.1 = getelementptr i8, ptr addrspace(5) %out, i32 185 %out.gep.2 = getelementptr i8, ptr addrspace(5) %out, i32 286 %out.gep.3 = getelementptr i8, ptr addrspace(5) %out, i32 387 88 store i8 9, ptr addrspace(5) %out, align 489 store i8 1, ptr addrspace(5) %out.gep.190 store i8 23, ptr addrspace(5) %out.gep.291 store i8 19, ptr addrspace(5) %out.gep.392 ret void93}94 95; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8_align1(96; ALIGNED: store i897; ALIGNED: store i898; ALIGNED: store i899; ALIGNED: store i8100 101; UNALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, ptr addrspace(5) %out, align 1102define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8_align1(ptr addrspace(5) %out) #0 {103 %out.gep.1 = getelementptr i8, ptr addrspace(5) %out, i32 1104 %out.gep.2 = getelementptr i8, ptr addrspace(5) %out, i32 2105 %out.gep.3 = getelementptr i8, ptr addrspace(5) %out, i32 3106 107 store i8 9, ptr addrspace(5) %out, align 1108 store i8 1, ptr addrspace(5) %out.gep.1, align 1109 store i8 23, ptr addrspace(5) %out.gep.2, align 1110 store i8 19, ptr addrspace(5) %out.gep.3, align 1111 ret void112}113 114; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16(115; ALL: store <2 x i16>116define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16(ptr addrspace(5) %out) #0 {117 %out.gep.1 = getelementptr i16, ptr addrspace(5) %out, i32 1118 119 store i16 9, ptr addrspace(5) %out, align 4120 store i16 12, ptr addrspace(5) %out.gep.1121 ret void122}123 124; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align2(125; ALIGNED: store i16126; ALIGNED: store i16127; UNALIGNED: store <2 x i16>128define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align2(ptr addrspace(5) %out) #0 {129 %out.gep.1 = getelementptr i16, ptr addrspace(5) %out, i32 1130 131 store i16 9, ptr addrspace(5) %out, align 2132 store i16 12, ptr addrspace(5) %out.gep.1, align 2133 ret void134}135 136; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align1(137; ALIGNED: store i16138; ALIGNED: store i16139 140; UNALIGNED: store <2 x i16> <i16 9, i16 12>, ptr addrspace(5) %out, align 1141define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align1(ptr addrspace(5) %out) #0 {142 %out.gep.1 = getelementptr i16, ptr addrspace(5) %out, i32 1143 144 store i16 9, ptr addrspace(5) %out, align 1145 store i16 12, ptr addrspace(5) %out.gep.1, align 1146 ret void147}148 149; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align8(150; ALL: store <2 x i16> <i16 9, i16 12>, ptr addrspace(5) %out, align 8151define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align8(ptr addrspace(5) %out) #0 {152 %out.gep.1 = getelementptr i16, ptr addrspace(5) %out, i32 1153 154 store i16 9, ptr addrspace(5) %out, align 8155 store i16 12, ptr addrspace(5) %out.gep.1, align 2156 ret void157}158 159; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32160; ELT4: store i32161; ELT4: store i32162; ELT4: store i32163 164; ELT8: store <2 x i32>165; ELT8: store i32166 167; ELT16: store <3 x i32>168define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32(ptr addrspace(5) %out) #0 {169 %out.gep.1 = getelementptr i32, ptr addrspace(5) %out, i32 1170 %out.gep.2 = getelementptr i32, ptr addrspace(5) %out, i32 2171 172 store i32 9, ptr addrspace(5) %out173 store i32 1, ptr addrspace(5) %out.gep.1174 store i32 23, ptr addrspace(5) %out.gep.2175 ret void176}177 178; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32_align1(179; ALIGNED: store i32180; ALIGNED: store i32181; ALIGNED: store i32182 183; ELT4-UNALIGNED: store i32184; ELT4-UNALIGNED: store i32185; ELT4-UNALIGNED: store i32186 187; ELT8-UNALIGNED: store <2 x i32>188; ELT8-UNALIGNED: store i32189 190; ELT16-UNALIGNED: store <3 x i32>191define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32_align1(ptr addrspace(5) %out) #0 {192 %out.gep.1 = getelementptr i32, ptr addrspace(5) %out, i32 1193 %out.gep.2 = getelementptr i32, ptr addrspace(5) %out, i32 2194 195 store i32 9, ptr addrspace(5) %out, align 1196 store i32 1, ptr addrspace(5) %out.gep.1, align 1197 store i32 23, ptr addrspace(5) %out.gep.2, align 1198 ret void199}200 201; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i8_align1(202; ALIGNED: store i8203; ALIGNED: store i8204; ALIGNED: store i8205 206; UNALIGNED: store <3 x i8>207define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i8_align1(ptr addrspace(5) %out) #0 {208 %out.gep.1 = getelementptr i8, ptr addrspace(5) %out, i8 1209 %out.gep.2 = getelementptr i8, ptr addrspace(5) %out, i8 2210 211 store i8 9, ptr addrspace(5) %out, align 1212 store i8 1, ptr addrspace(5) %out.gep.1, align 1213 store i8 23, ptr addrspace(5) %out.gep.2, align 1214 ret void215}216 217attributes #0 = { nounwind }218