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1; RUN: opt -mtriple=amdgcn-amd-amdhsa --mcpu=hawaii -passes=load-store-vectorizer -S -o - %s | FileCheck %s2; Copy of test/CodeGen/AMDGPU/merge-stores.ll with some additions3 4; TODO: Vector element tests5; TODO: Non-zero base offset for load and store combinations6; TODO: Same base addrspacecasted7 8 9define amdgpu_kernel void @merge_global_store_2_constants_i8(ptr addrspace(1) %out) #0 {10; CHECK-LABEL: @merge_global_store_2_constants_i8(11; CHECK-NEXT: store <2 x i8> <i8 -56, i8 123>, ptr addrspace(1) [[OUT:%.*]], align 212; CHECK-NEXT: ret void13;14 %out.gep.1 = getelementptr i8, ptr addrspace(1) %out, i32 115 16 store i8 123, ptr addrspace(1) %out.gep.117 store i8 456, ptr addrspace(1) %out, align 218 ret void19}20 21define amdgpu_kernel void @merge_global_store_2_constants_i8_natural_align(ptr addrspace(1) %out) #0 {22; CHECK-LABEL: @merge_global_store_2_constants_i8_natural_align(23; CHECK-NEXT: store <2 x i8> <i8 -56, i8 123>, ptr addrspace(1) [[OUT:%.*]], align 124; CHECK-NEXT: ret void25;26 %out.gep.1 = getelementptr i8, ptr addrspace(1) %out, i32 127 28 store i8 123, ptr addrspace(1) %out.gep.129 store i8 456, ptr addrspace(1) %out30 ret void31}32 33define amdgpu_kernel void @merge_global_store_2_constants_i16(ptr addrspace(1) %out) #0 {34; CHECK-LABEL: @merge_global_store_2_constants_i16(35; CHECK-NEXT: store <2 x i16> <i16 456, i16 123>, ptr addrspace(1) [[OUT:%.*]], align 436; CHECK-NEXT: ret void37;38 %out.gep.1 = getelementptr i16, ptr addrspace(1) %out, i32 139 40 store i16 123, ptr addrspace(1) %out.gep.141 store i16 456, ptr addrspace(1) %out, align 442 ret void43}44 45define amdgpu_kernel void @merge_global_store_2_constants_0_i16(ptr addrspace(1) %out) #0 {46; CHECK-LABEL: @merge_global_store_2_constants_0_i16(47; CHECK-NEXT: store <2 x i16> zeroinitializer, ptr addrspace(1) [[OUT:%.*]], align 448; CHECK-NEXT: ret void49;50 %out.gep.1 = getelementptr i16, ptr addrspace(1) %out, i32 151 52 store i16 0, ptr addrspace(1) %out.gep.153 store i16 0, ptr addrspace(1) %out, align 454 ret void55}56 57define amdgpu_kernel void @merge_global_store_2_constants_i16_natural_align(ptr addrspace(1) %out) #0 {58; CHECK-LABEL: @merge_global_store_2_constants_i16_natural_align(59; CHECK-NEXT: store <2 x i16> <i16 456, i16 123>, ptr addrspace(1) [[OUT:%.*]], align 260; CHECK-NEXT: ret void61;62 %out.gep.1 = getelementptr i16, ptr addrspace(1) %out, i32 163 64 store i16 123, ptr addrspace(1) %out.gep.165 store i16 456, ptr addrspace(1) %out66 ret void67}68 69define amdgpu_kernel void @merge_global_store_2_constants_i16_align_1(ptr addrspace(1) %out) #0 {70; CHECK-LABEL: @merge_global_store_2_constants_i16_align_1(71; CHECK-NEXT: store <2 x i16> <i16 456, i16 123>, ptr addrspace(1) [[OUT:%.*]], align 172; CHECK-NEXT: ret void73;74 %out.gep.1 = getelementptr i16, ptr addrspace(1) %out, i32 175 76 store i16 123, ptr addrspace(1) %out.gep.1, align 177 store i16 456, ptr addrspace(1) %out, align 178 ret void79}80 81define amdgpu_kernel void @merge_global_store_2_constants_half_natural_align(ptr addrspace(1) %out) #0 {82; CHECK-LABEL: @merge_global_store_2_constants_half_natural_align(83; CHECK-NEXT: store <2 x half> <half 0xH3C00, half 0xH4000>, ptr addrspace(1) [[OUT:%.*]], align 284; CHECK-NEXT: ret void85;86 %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 187 88 store half 2.0, ptr addrspace(1) %out.gep.189 store half 1.0, ptr addrspace(1) %out90 ret void91}92 93define amdgpu_kernel void @merge_global_store_2_constants_half_align_1(ptr addrspace(1) %out) #0 {94; CHECK-LABEL: @merge_global_store_2_constants_half_align_1(95; CHECK-NEXT: store <2 x half> <half 0xH3C00, half 0xH4000>, ptr addrspace(1) [[OUT:%.*]], align 196; CHECK-NEXT: ret void97;98 %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 199 100 store half 2.0, ptr addrspace(1) %out.gep.1, align 1101 store half 1.0, ptr addrspace(1) %out, align 1102 ret void103}104 105define amdgpu_kernel void @merge_global_store_2_constants_i32(ptr addrspace(1) %out) #0 {106; CHECK-LABEL: @merge_global_store_2_constants_i32(107; CHECK-NEXT: store <2 x i32> <i32 456, i32 123>, ptr addrspace(1) [[OUT:%.*]], align 4108; CHECK-NEXT: ret void109;110 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1111 112 store i32 123, ptr addrspace(1) %out.gep.1113 store i32 456, ptr addrspace(1) %out114 ret void115}116 117define amdgpu_kernel void @merge_global_store_2_constants_i32_f32(ptr addrspace(1) %out) #0 {118; CHECK-LABEL: @merge_global_store_2_constants_i32_f32(119; CHECK-NEXT: store <2 x i32> <i32 456, i32 1065353216>, ptr addrspace(1) [[OUT:%.*]], align 4120; CHECK-NEXT: ret void121;122 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1123 store float 1.0, ptr addrspace(1) %out.gep.1124 store i32 456, ptr addrspace(1) %out125 ret void126}127 128define amdgpu_kernel void @merge_global_store_2_constants_f32_i32(ptr addrspace(1) %out) #0 {129; CHECK-LABEL: @merge_global_store_2_constants_f32_i32(130; CHECK-NEXT: store <2 x i32> <i32 1082130432, i32 123>, ptr addrspace(1) [[OUT:%.*]], align 4131; CHECK-NEXT: ret void132;133 %out.gep.1 = getelementptr float, ptr addrspace(1) %out, i32 1134 store i32 123, ptr addrspace(1) %out.gep.1135 store float 4.0, ptr addrspace(1) %out136 ret void137}138 139define amdgpu_kernel void @merge_global_store_4_constants_i32(ptr addrspace(1) %out) #0 {140; CHECK-LABEL: @merge_global_store_4_constants_i32(141; CHECK-NEXT: store <4 x i32> <i32 1234, i32 123, i32 456, i32 333>, ptr addrspace(1) [[OUT:%.*]], align 4142; CHECK-NEXT: ret void143;144 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1145 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2146 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 3147 148 store i32 123, ptr addrspace(1) %out.gep.1149 store i32 456, ptr addrspace(1) %out.gep.2150 store i32 333, ptr addrspace(1) %out.gep.3151 store i32 1234, ptr addrspace(1) %out152 ret void153}154 155define amdgpu_kernel void @merge_global_store_4_constants_f32_order(ptr addrspace(1) %out) #0 {156; CHECK-LABEL: @merge_global_store_4_constants_f32_order(157; CHECK-NEXT: store <4 x float> <float 8.000000e+00, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>, ptr addrspace(1) [[OUT:%.*]], align 4158; CHECK-NEXT: ret void159;160 %out.gep.1 = getelementptr float, ptr addrspace(1) %out, i32 1161 %out.gep.2 = getelementptr float, ptr addrspace(1) %out, i32 2162 %out.gep.3 = getelementptr float, ptr addrspace(1) %out, i32 3163 164 store float 8.0, ptr addrspace(1) %out165 store float 1.0, ptr addrspace(1) %out.gep.1166 store float 2.0, ptr addrspace(1) %out.gep.2167 store float 4.0, ptr addrspace(1) %out.gep.3168 ret void169}170 171; First store is out of order.172define amdgpu_kernel void @merge_global_store_4_constants_f32(ptr addrspace(1) %out) #0 {173; CHECK-LABEL: @merge_global_store_4_constants_f32(174; CHECK-NEXT: store <4 x float> <float 8.000000e+00, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>, ptr addrspace(1) [[OUT:%.*]], align 4175; CHECK-NEXT: ret void176;177 %out.gep.1 = getelementptr float, ptr addrspace(1) %out, i32 1178 %out.gep.2 = getelementptr float, ptr addrspace(1) %out, i32 2179 %out.gep.3 = getelementptr float, ptr addrspace(1) %out, i32 3180 181 store float 1.0, ptr addrspace(1) %out.gep.1182 store float 2.0, ptr addrspace(1) %out.gep.2183 store float 4.0, ptr addrspace(1) %out.gep.3184 store float 8.0, ptr addrspace(1) %out185 ret void186}187 188define amdgpu_kernel void @merge_global_store_4_constants_mixed_i32_f32(ptr addrspace(1) %out) #0 {189; CHECK-LABEL: @merge_global_store_4_constants_mixed_i32_f32(190; CHECK-NEXT: store <4 x i32> <i32 1090519040, i32 11, i32 1073741824, i32 17>, ptr addrspace(1) [[OUT:%.*]], align 4191; CHECK-NEXT: ret void192;193 %out.gep.1 = getelementptr float, ptr addrspace(1) %out, i32 1194 %out.gep.2 = getelementptr float, ptr addrspace(1) %out, i32 2195 %out.gep.3 = getelementptr float, ptr addrspace(1) %out, i32 3196 197 198 store i32 11, ptr addrspace(1) %out.gep.1199 store float 2.0, ptr addrspace(1) %out.gep.2200 store i32 17, ptr addrspace(1) %out.gep.3201 store float 8.0, ptr addrspace(1) %out202 ret void203}204 205define amdgpu_kernel void @merge_global_store_3_constants_i32(ptr addrspace(1) %out) #0 {206; CHECK-LABEL: @merge_global_store_3_constants_i32(207; CHECK-NEXT: store <3 x i32> <i32 1234, i32 123, i32 456>, ptr addrspace(1) [[OUT:%.*]], align 4208; CHECK-NEXT: ret void209;210 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1211 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2212 213 store i32 123, ptr addrspace(1) %out.gep.1214 store i32 456, ptr addrspace(1) %out.gep.2215 store i32 1234, ptr addrspace(1) %out216 ret void217}218 219define amdgpu_kernel void @merge_global_store_2_constants_i64(ptr addrspace(1) %out) #0 {220; CHECK-LABEL: @merge_global_store_2_constants_i64(221; CHECK-NEXT: store <2 x i64> <i64 456, i64 123>, ptr addrspace(1) [[OUT:%.*]], align 8222; CHECK-NEXT: ret void223;224 %out.gep.1 = getelementptr i64, ptr addrspace(1) %out, i64 1225 226 store i64 123, ptr addrspace(1) %out.gep.1227 store i64 456, ptr addrspace(1) %out228 ret void229}230 231define amdgpu_kernel void @merge_global_store_4_constants_i64(ptr addrspace(1) %out) #0 {232; CHECK-LABEL: @merge_global_store_4_constants_i64(233; CHECK-NEXT: [[OUT_GEP_2:%.*]] = getelementptr i64, ptr addrspace(1) [[OUT:%.*]], i64 2234; CHECK-NEXT: store <2 x i64> <i64 456, i64 333>, ptr addrspace(1) [[OUT_GEP_2]], align 8235; CHECK-NEXT: store <2 x i64> <i64 1234, i64 123>, ptr addrspace(1) [[OUT]], align 8236; CHECK-NEXT: ret void237;238 %out.gep.1 = getelementptr i64, ptr addrspace(1) %out, i64 1239 %out.gep.2 = getelementptr i64, ptr addrspace(1) %out, i64 2240 %out.gep.3 = getelementptr i64, ptr addrspace(1) %out, i64 3241 242 store i64 123, ptr addrspace(1) %out.gep.1243 store i64 456, ptr addrspace(1) %out.gep.2244 store i64 333, ptr addrspace(1) %out.gep.3245 store i64 1234, ptr addrspace(1) %out246 ret void247}248 249define amdgpu_kernel void @merge_global_store_2_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {250; CHECK-LABEL: @merge_global_store_2_adjacent_loads_i32(251; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN:%.*]], align 4252; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0253; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1254; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i32 0255; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i32 1256; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 4257; CHECK-NEXT: ret void258;259 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1260 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1261 262 %lo = load i32, ptr addrspace(1) %in263 %hi = load i32, ptr addrspace(1) %in.gep.1264 265 store i32 %lo, ptr addrspace(1) %out266 store i32 %hi, ptr addrspace(1) %out.gep.1267 ret void268}269 270define amdgpu_kernel void @merge_global_store_2_adjacent_loads_i32_nonzero_base(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {271; CHECK-LABEL: @merge_global_store_2_adjacent_loads_i32_nonzero_base(272; CHECK-NEXT: [[IN_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[IN:%.*]], i32 2273; CHECK-NEXT: [[OUT_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT:%.*]], i32 2274; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN_GEP_0]], align 4275; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0276; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1277; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i32 0278; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i32 1279; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT_GEP_0]], align 4280; CHECK-NEXT: ret void281;282 %in.gep.0 = getelementptr i32, ptr addrspace(1) %in, i32 2283 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 3284 285 %out.gep.0 = getelementptr i32, ptr addrspace(1) %out, i32 2286 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 3287 %lo = load i32, ptr addrspace(1) %in.gep.0288 %hi = load i32, ptr addrspace(1) %in.gep.1289 290 store i32 %lo, ptr addrspace(1) %out.gep.0291 store i32 %hi, ptr addrspace(1) %out.gep.1292 ret void293}294 295define amdgpu_kernel void @merge_global_store_2_adjacent_loads_shuffle_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {296; CHECK-LABEL: @merge_global_store_2_adjacent_loads_shuffle_i32(297; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN:%.*]], align 4298; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0299; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1300; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[HI2]], i32 0301; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[LO1]], i32 1302; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 4303; CHECK-NEXT: ret void304;305 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1306 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1307 308 %lo = load i32, ptr addrspace(1) %in309 %hi = load i32, ptr addrspace(1) %in.gep.1310 311 store i32 %hi, ptr addrspace(1) %out312 store i32 %lo, ptr addrspace(1) %out.gep.1313 ret void314}315 316define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {317; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i32(318; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4319; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0320; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1321; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2322; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3323; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0324; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1325; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2326; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3327; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4328; CHECK-NEXT: ret void329;330 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1331 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2332 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 3333 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1334 %in.gep.2 = getelementptr i32, ptr addrspace(1) %in, i32 2335 %in.gep.3 = getelementptr i32, ptr addrspace(1) %in, i32 3336 337 %x = load i32, ptr addrspace(1) %in338 %y = load i32, ptr addrspace(1) %in.gep.1339 %z = load i32, ptr addrspace(1) %in.gep.2340 %w = load i32, ptr addrspace(1) %in.gep.3341 342 store i32 %x, ptr addrspace(1) %out343 store i32 %y, ptr addrspace(1) %out.gep.1344 store i32 %z, ptr addrspace(1) %out.gep.2345 store i32 %w, ptr addrspace(1) %out.gep.3346 ret void347}348 349define amdgpu_kernel void @merge_global_store_3_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {350; CHECK-LABEL: @merge_global_store_3_adjacent_loads_i32(351; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr addrspace(1) [[IN:%.*]], align 4352; CHECK-NEXT: [[X1:%.*]] = extractelement <3 x i32> [[TMP1]], i32 0353; CHECK-NEXT: [[Y2:%.*]] = extractelement <3 x i32> [[TMP1]], i32 1354; CHECK-NEXT: [[Z3:%.*]] = extractelement <3 x i32> [[TMP1]], i32 2355; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[X1]], i32 0356; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[Y2]], i32 1357; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[Z3]], i32 2358; CHECK-NEXT: store <3 x i32> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4359; CHECK-NEXT: ret void360;361 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1362 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2363 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1364 %in.gep.2 = getelementptr i32, ptr addrspace(1) %in, i32 2365 366 %x = load i32, ptr addrspace(1) %in367 %y = load i32, ptr addrspace(1) %in.gep.1368 %z = load i32, ptr addrspace(1) %in.gep.2369 370 store i32 %x, ptr addrspace(1) %out371 store i32 %y, ptr addrspace(1) %out.gep.1372 store i32 %z, ptr addrspace(1) %out.gep.2373 ret void374}375 376define amdgpu_kernel void @merge_global_store_4_adjacent_loads_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {377; CHECK-LABEL: @merge_global_store_4_adjacent_loads_f32(378; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(1) [[IN:%.*]], align 4379; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[TMP1]], i32 0380; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x float> [[TMP1]], i32 1381; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x float> [[TMP1]], i32 2382; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x float> [[TMP1]], i32 3383; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[X1]], i32 0384; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[Y2]], i32 1385; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[Z3]], i32 2386; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[W4]], i32 3387; CHECK-NEXT: store <4 x float> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4388; CHECK-NEXT: ret void389;390 %out.gep.1 = getelementptr float, ptr addrspace(1) %out, i32 1391 %out.gep.2 = getelementptr float, ptr addrspace(1) %out, i32 2392 %out.gep.3 = getelementptr float, ptr addrspace(1) %out, i32 3393 %in.gep.1 = getelementptr float, ptr addrspace(1) %in, i32 1394 %in.gep.2 = getelementptr float, ptr addrspace(1) %in, i32 2395 %in.gep.3 = getelementptr float, ptr addrspace(1) %in, i32 3396 397 %x = load float, ptr addrspace(1) %in398 %y = load float, ptr addrspace(1) %in.gep.1399 %z = load float, ptr addrspace(1) %in.gep.2400 %w = load float, ptr addrspace(1) %in.gep.3401 402 store float %x, ptr addrspace(1) %out403 store float %y, ptr addrspace(1) %out.gep.1404 store float %z, ptr addrspace(1) %out.gep.2405 store float %w, ptr addrspace(1) %out.gep.3406 ret void407}408 409define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32_nonzero_base(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {410; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i32_nonzero_base(411; CHECK-NEXT: [[IN_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[IN:%.*]], i32 11412; CHECK-NEXT: [[OUT_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT:%.*]], i32 7413; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN_GEP_0]], align 4414; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0415; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1416; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2417; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3418; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0419; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1420; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2421; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3422; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT_GEP_0]], align 4423; CHECK-NEXT: ret void424;425 %in.gep.0 = getelementptr i32, ptr addrspace(1) %in, i32 11426 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 12427 %in.gep.2 = getelementptr i32, ptr addrspace(1) %in, i32 13428 %in.gep.3 = getelementptr i32, ptr addrspace(1) %in, i32 14429 %out.gep.0 = getelementptr i32, ptr addrspace(1) %out, i32 7430 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 8431 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 9432 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 10433 434 %x = load i32, ptr addrspace(1) %in.gep.0435 %y = load i32, ptr addrspace(1) %in.gep.1436 %z = load i32, ptr addrspace(1) %in.gep.2437 %w = load i32, ptr addrspace(1) %in.gep.3438 439 store i32 %x, ptr addrspace(1) %out.gep.0440 store i32 %y, ptr addrspace(1) %out.gep.1441 store i32 %z, ptr addrspace(1) %out.gep.2442 store i32 %w, ptr addrspace(1) %out.gep.3443 ret void444}445 446define amdgpu_kernel void @merge_global_store_4_adjacent_loads_inverse_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {447; CHECK-LABEL: @merge_global_store_4_adjacent_loads_inverse_i32(448; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4449; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0450; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1451; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2452; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3453; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() #[[ATTR3:[0-9]+]]454; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0455; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1456; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2457; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3458; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4459; CHECK-NEXT: ret void460;461 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1462 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2463 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 3464 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1465 %in.gep.2 = getelementptr i32, ptr addrspace(1) %in, i32 2466 %in.gep.3 = getelementptr i32, ptr addrspace(1) %in, i32 3467 468 %x = load i32, ptr addrspace(1) %in469 %y = load i32, ptr addrspace(1) %in.gep.1470 %z = load i32, ptr addrspace(1) %in.gep.2471 %w = load i32, ptr addrspace(1) %in.gep.3472 473 ; Make sure the barrier doesn't stop this474 tail call void @llvm.amdgcn.s.barrier() #1475 476 store i32 %w, ptr addrspace(1) %out.gep.3477 store i32 %z, ptr addrspace(1) %out.gep.2478 store i32 %y, ptr addrspace(1) %out.gep.1479 store i32 %x, ptr addrspace(1) %out480 481 ret void482}483 484define amdgpu_kernel void @merge_global_store_4_adjacent_loads_shuffle_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {485; CHECK-LABEL: @merge_global_store_4_adjacent_loads_shuffle_i32(486; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4487; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0488; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1489; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2490; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3491; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() #[[ATTR3]]492; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[W4]], i32 0493; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z3]], i32 1494; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Y2]], i32 2495; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[X1]], i32 3496; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4497; CHECK-NEXT: ret void498;499 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1500 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2501 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 3502 %in.gep.1 = getelementptr i32, ptr addrspace(1) %in, i32 1503 %in.gep.2 = getelementptr i32, ptr addrspace(1) %in, i32 2504 %in.gep.3 = getelementptr i32, ptr addrspace(1) %in, i32 3505 506 %x = load i32, ptr addrspace(1) %in507 %y = load i32, ptr addrspace(1) %in.gep.1508 %z = load i32, ptr addrspace(1) %in.gep.2509 %w = load i32, ptr addrspace(1) %in.gep.3510 511 ; Make sure the barrier doesn't stop this512 tail call void @llvm.amdgcn.s.barrier() #1513 514 store i32 %w, ptr addrspace(1) %out515 store i32 %z, ptr addrspace(1) %out.gep.1516 store i32 %y, ptr addrspace(1) %out.gep.2517 store i32 %x, ptr addrspace(1) %out.gep.3518 519 ret void520}521 522define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {523; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i8(524; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(1) [[IN:%.*]], align 4525; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0526; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1527; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2528; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3529; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i32 0530; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i32 1531; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i32 2532; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i32 3533; CHECK-NEXT: store <4 x i8> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4534; CHECK-NEXT: ret void535;536 %out.gep.1 = getelementptr i8, ptr addrspace(1) %out, i8 1537 %out.gep.2 = getelementptr i8, ptr addrspace(1) %out, i8 2538 %out.gep.3 = getelementptr i8, ptr addrspace(1) %out, i8 3539 %in.gep.1 = getelementptr i8, ptr addrspace(1) %in, i8 1540 %in.gep.2 = getelementptr i8, ptr addrspace(1) %in, i8 2541 %in.gep.3 = getelementptr i8, ptr addrspace(1) %in, i8 3542 543 %x = load i8, ptr addrspace(1) %in, align 4544 %y = load i8, ptr addrspace(1) %in.gep.1545 %z = load i8, ptr addrspace(1) %in.gep.2546 %w = load i8, ptr addrspace(1) %in.gep.3547 548 store i8 %x, ptr addrspace(1) %out, align 4549 store i8 %y, ptr addrspace(1) %out.gep.1550 store i8 %z, ptr addrspace(1) %out.gep.2551 store i8 %w, ptr addrspace(1) %out.gep.3552 ret void553}554 555define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i8_natural_align(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {556; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i8_natural_align(557; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(1) [[IN:%.*]], align 1558; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0559; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1560; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2561; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3562; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i32 0563; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i32 1564; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i32 2565; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i32 3566; CHECK-NEXT: store <4 x i8> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 1567; CHECK-NEXT: ret void568;569 %out.gep.1 = getelementptr i8, ptr addrspace(1) %out, i8 1570 %out.gep.2 = getelementptr i8, ptr addrspace(1) %out, i8 2571 %out.gep.3 = getelementptr i8, ptr addrspace(1) %out, i8 3572 %in.gep.1 = getelementptr i8, ptr addrspace(1) %in, i8 1573 %in.gep.2 = getelementptr i8, ptr addrspace(1) %in, i8 2574 %in.gep.3 = getelementptr i8, ptr addrspace(1) %in, i8 3575 576 %x = load i8, ptr addrspace(1) %in577 %y = load i8, ptr addrspace(1) %in.gep.1578 %z = load i8, ptr addrspace(1) %in.gep.2579 %w = load i8, ptr addrspace(1) %in.gep.3580 581 store i8 %x, ptr addrspace(1) %out582 store i8 %y, ptr addrspace(1) %out.gep.1583 store i8 %z, ptr addrspace(1) %out.gep.2584 store i8 %w, ptr addrspace(1) %out.gep.3585 ret void586}587 588define amdgpu_kernel void @merge_global_store_4_vector_elts_loads_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {589; CHECK-LABEL: @merge_global_store_4_vector_elts_loads_v4i32(590; CHECK-NEXT: [[VEC:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 16591; CHECK-NEXT: [[X:%.*]] = extractelement <4 x i32> [[VEC]], i32 0592; CHECK-NEXT: [[Y:%.*]] = extractelement <4 x i32> [[VEC]], i32 1593; CHECK-NEXT: [[Z:%.*]] = extractelement <4 x i32> [[VEC]], i32 2594; CHECK-NEXT: [[W:%.*]] = extractelement <4 x i32> [[VEC]], i32 3595; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0596; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[Y]], i32 1597; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z]], i32 2598; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[W]], i32 3599; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4600; CHECK-NEXT: ret void601;602 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1603 %out.gep.2 = getelementptr i32, ptr addrspace(1) %out, i32 2604 %out.gep.3 = getelementptr i32, ptr addrspace(1) %out, i32 3605 %vec = load <4 x i32>, ptr addrspace(1) %in606 607 %x = extractelement <4 x i32> %vec, i32 0608 %y = extractelement <4 x i32> %vec, i32 1609 %z = extractelement <4 x i32> %vec, i32 2610 %w = extractelement <4 x i32> %vec, i32 3611 612 store i32 %x, ptr addrspace(1) %out613 store i32 %y, ptr addrspace(1) %out.gep.1614 store i32 %z, ptr addrspace(1) %out.gep.2615 store i32 %w, ptr addrspace(1) %out.gep.3616 ret void617}618 619define amdgpu_kernel void @merge_local_store_2_constants_i8(ptr addrspace(3) %out) #0 {620; CHECK-LABEL: @merge_local_store_2_constants_i8(621; CHECK-NEXT: store <2 x i8> <i8 -56, i8 123>, ptr addrspace(3) [[OUT:%.*]], align 2622; CHECK-NEXT: ret void623;624 %out.gep.1 = getelementptr i8, ptr addrspace(3) %out, i32 1625 626 store i8 123, ptr addrspace(3) %out.gep.1627 store i8 456, ptr addrspace(3) %out, align 2628 ret void629}630 631define amdgpu_kernel void @merge_local_store_2_constants_i32(ptr addrspace(3) %out) #0 {632; CHECK-LABEL: @merge_local_store_2_constants_i32(633; CHECK-NEXT: store <2 x i32> <i32 456, i32 123>, ptr addrspace(3) [[OUT:%.*]], align 4634; CHECK-NEXT: ret void635;636 %out.gep.1 = getelementptr i32, ptr addrspace(3) %out, i32 1637 638 store i32 123, ptr addrspace(3) %out.gep.1639 store i32 456, ptr addrspace(3) %out640 ret void641}642 643define amdgpu_kernel void @merge_local_store_2_constants_i32_align_2(ptr addrspace(3) %out) #0 {644; CHECK-LABEL: @merge_local_store_2_constants_i32_align_2(645; CHECK-NEXT: [[OUT_GEP_1:%.*]] = getelementptr i32, ptr addrspace(3) [[OUT:%.*]], i32 1646; CHECK-NEXT: store i32 123, ptr addrspace(3) [[OUT_GEP_1]], align 2647; CHECK-NEXT: store i32 456, ptr addrspace(3) [[OUT]], align 2648; CHECK-NEXT: ret void649;650 %out.gep.1 = getelementptr i32, ptr addrspace(3) %out, i32 1651 652 store i32 123, ptr addrspace(3) %out.gep.1, align 2653 store i32 456, ptr addrspace(3) %out, align 2654 ret void655}656 657define amdgpu_kernel void @merge_local_store_4_constants_i32(ptr addrspace(3) %out) #0 {658; CHECK-LABEL: @merge_local_store_4_constants_i32(659; CHECK-NEXT: [[OUT_GEP_2:%.*]] = getelementptr i32, ptr addrspace(3) [[OUT:%.*]], i32 2660; CHECK-NEXT: store <2 x i32> <i32 456, i32 333>, ptr addrspace(3) [[OUT_GEP_2]], align 4661; CHECK-NEXT: store <2 x i32> <i32 1234, i32 123>, ptr addrspace(3) [[OUT]], align 4662; CHECK-NEXT: ret void663;664 %out.gep.1 = getelementptr i32, ptr addrspace(3) %out, i32 1665 %out.gep.2 = getelementptr i32, ptr addrspace(3) %out, i32 2666 %out.gep.3 = getelementptr i32, ptr addrspace(3) %out, i32 3667 668 store i32 123, ptr addrspace(3) %out.gep.1669 store i32 456, ptr addrspace(3) %out.gep.2670 store i32 333, ptr addrspace(3) %out.gep.3671 store i32 1234, ptr addrspace(3) %out672 ret void673}674 675define amdgpu_kernel void @merge_global_store_5_constants_i32(ptr addrspace(1) %out) {676; CHECK-LABEL: @merge_global_store_5_constants_i32(677; CHECK-NEXT: store <4 x i32> <i32 9, i32 12, i32 16, i32 -12>, ptr addrspace(1) [[OUT:%.*]], align 4678; CHECK-NEXT: [[IDX4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT]], i64 4679; CHECK-NEXT: store i32 11, ptr addrspace(1) [[IDX4]], align 4680; CHECK-NEXT: ret void681;682 store i32 9, ptr addrspace(1) %out, align 4683 %idx1 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1684 store i32 12, ptr addrspace(1) %idx1, align 4685 %idx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 2686 store i32 16, ptr addrspace(1) %idx2, align 4687 %idx3 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 3688 store i32 -12, ptr addrspace(1) %idx3, align 4689 %idx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 4690 store i32 11, ptr addrspace(1) %idx4, align 4691 ret void692}693 694define amdgpu_kernel void @merge_global_store_6_constants_i32(ptr addrspace(1) %out) {695; CHECK-LABEL: @merge_global_store_6_constants_i32(696; CHECK-NEXT: store <4 x i32> <i32 13, i32 15, i32 62, i32 63>, ptr addrspace(1) [[OUT:%.*]], align 4697; CHECK-NEXT: [[IDX4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT]], i64 4698; CHECK-NEXT: store <2 x i32> <i32 11, i32 123>, ptr addrspace(1) [[IDX4]], align 4699; CHECK-NEXT: ret void700;701 store i32 13, ptr addrspace(1) %out, align 4702 %idx1 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1703 store i32 15, ptr addrspace(1) %idx1, align 4704 %idx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 2705 store i32 62, ptr addrspace(1) %idx2, align 4706 %idx3 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 3707 store i32 63, ptr addrspace(1) %idx3, align 4708 %idx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 4709 store i32 11, ptr addrspace(1) %idx4, align 4710 %idx5 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 5711 store i32 123, ptr addrspace(1) %idx5, align 4712 ret void713}714 715define amdgpu_kernel void @merge_global_store_7_constants_i32(ptr addrspace(1) %out) {716; CHECK-LABEL: @merge_global_store_7_constants_i32(717; CHECK-NEXT: store <4 x i32> <i32 34, i32 999, i32 65, i32 33>, ptr addrspace(1) [[OUT:%.*]], align 4718; CHECK-NEXT: [[IDX4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT]], i64 4719; CHECK-NEXT: store <3 x i32> <i32 98, i32 91, i32 212>, ptr addrspace(1) [[IDX4]], align 4720; CHECK-NEXT: ret void721;722 store i32 34, ptr addrspace(1) %out, align 4723 %idx1 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1724 store i32 999, ptr addrspace(1) %idx1, align 4725 %idx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 2726 store i32 65, ptr addrspace(1) %idx2, align 4727 %idx3 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 3728 store i32 33, ptr addrspace(1) %idx3, align 4729 %idx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 4730 store i32 98, ptr addrspace(1) %idx4, align 4731 %idx5 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 5732 store i32 91, ptr addrspace(1) %idx5, align 4733 %idx6 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 6734 store i32 212, ptr addrspace(1) %idx6, align 4735 ret void736}737 738define amdgpu_kernel void @merge_global_store_8_constants_i32(ptr addrspace(1) %out) {739; CHECK-LABEL: @merge_global_store_8_constants_i32(740; CHECK-NEXT: store <4 x i32> <i32 34, i32 999, i32 65, i32 33>, ptr addrspace(1) [[OUT:%.*]], align 4741; CHECK-NEXT: [[IDX4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT]], i64 4742; CHECK-NEXT: store <4 x i32> <i32 98, i32 91, i32 212, i32 999>, ptr addrspace(1) [[IDX4]], align 4743; CHECK-NEXT: ret void744;745 store i32 34, ptr addrspace(1) %out, align 4746 %idx1 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1747 store i32 999, ptr addrspace(1) %idx1, align 4748 %idx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 2749 store i32 65, ptr addrspace(1) %idx2, align 4750 %idx3 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 3751 store i32 33, ptr addrspace(1) %idx3, align 4752 %idx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 4753 store i32 98, ptr addrspace(1) %idx4, align 4754 %idx5 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 5755 store i32 91, ptr addrspace(1) %idx5, align 4756 %idx6 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 6757 store i32 212, ptr addrspace(1) %idx6, align 4758 %idx7 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 7759 store i32 999, ptr addrspace(1) %idx7, align 4760 ret void761}762 763define amdgpu_kernel void @copy_v3i32_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {764; CHECK-LABEL: @copy_v3i32_align4(765; CHECK-NEXT: [[VEC:%.*]] = load <3 x i32>, ptr addrspace(1) [[IN:%.*]], align 4766; CHECK-NEXT: store <3 x i32> [[VEC]], ptr addrspace(1) [[OUT:%.*]], align 16767; CHECK-NEXT: ret void768;769 %vec = load <3 x i32>, ptr addrspace(1) %in, align 4770 store <3 x i32> %vec, ptr addrspace(1) %out771 ret void772}773 774define amdgpu_kernel void @copy_v3i64_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {775; CHECK-LABEL: @copy_v3i64_align4(776; CHECK-NEXT: [[VEC:%.*]] = load <3 x i64>, ptr addrspace(1) [[IN:%.*]], align 4777; CHECK-NEXT: store <3 x i64> [[VEC]], ptr addrspace(1) [[OUT:%.*]], align 32778; CHECK-NEXT: ret void779;780 %vec = load <3 x i64>, ptr addrspace(1) %in, align 4781 store <3 x i64> %vec, ptr addrspace(1) %out782 ret void783}784 785define amdgpu_kernel void @copy_v3f32_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {786; CHECK-LABEL: @copy_v3f32_align4(787; CHECK-NEXT: [[VEC:%.*]] = load <3 x float>, ptr addrspace(1) [[IN:%.*]], align 4788; CHECK-NEXT: [[FADD:%.*]] = fadd <3 x float> [[VEC]], <float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>789; CHECK-NEXT: store <3 x float> [[FADD]], ptr addrspace(1) [[OUT:%.*]], align 16790; CHECK-NEXT: ret void791;792 %vec = load <3 x float>, ptr addrspace(1) %in, align 4793 %fadd = fadd <3 x float> %vec, <float 1.0, float 2.0, float 4.0>794 store <3 x float> %fadd, ptr addrspace(1) %out795 ret void796}797 798define amdgpu_kernel void @copy_v3f64_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {799; CHECK-LABEL: @copy_v3f64_align4(800; CHECK-NEXT: [[VEC:%.*]] = load <3 x double>, ptr addrspace(1) [[IN:%.*]], align 4801; CHECK-NEXT: [[FADD:%.*]] = fadd <3 x double> [[VEC]], <double 1.000000e+00, double 2.000000e+00, double 4.000000e+00>802; CHECK-NEXT: store <3 x double> [[FADD]], ptr addrspace(1) [[OUT:%.*]], align 32803; CHECK-NEXT: ret void804;805 %vec = load <3 x double>, ptr addrspace(1) %in, align 4806 %fadd = fadd <3 x double> %vec, <double 1.0, double 2.0, double 4.0>807 store <3 x double> %fadd, ptr addrspace(1) %out808 ret void809}810 811; Verify that we no longer hit asserts for this test case. No change expected.812define amdgpu_kernel void @copy_vec_of_ptrs(ptr addrspace(1) %out,813; CHECK-LABEL: @copy_vec_of_ptrs(814; CHECK-NEXT: [[IN_GEP_1:%.*]] = getelementptr <2 x ptr>, ptr addrspace(1) [[IN:%.*]], i32 1815; CHECK-NEXT: [[VEC1:%.*]] = load <2 x ptr>, ptr addrspace(1) [[IN_GEP_1]], align 16816; CHECK-NEXT: [[VEC2:%.*]] = load <2 x ptr>, ptr addrspace(1) [[IN]], align 4817; CHECK-NEXT: [[OUT_GEP_1:%.*]] = getelementptr <2 x ptr>, ptr addrspace(1) [[OUT:%.*]], i32 1818; CHECK-NEXT: store <2 x ptr> [[VEC1]], ptr addrspace(1) [[OUT_GEP_1]], align 16819; CHECK-NEXT: store <2 x ptr> [[VEC2]], ptr addrspace(1) [[OUT]], align 4820; CHECK-NEXT: ret void821;822 ptr addrspace(1) %in ) #0 {823 %in.gep.1 = getelementptr <2 x ptr>, ptr addrspace(1) %in, i32 1824 %vec1 = load <2 x ptr>, ptr addrspace(1) %in.gep.1825 %vec2 = load <2 x ptr>, ptr addrspace(1) %in, align 4826 827 %out.gep.1 = getelementptr <2 x ptr>, ptr addrspace(1) %out, i32 1828 store <2 x ptr> %vec1, ptr addrspace(1) %out.gep.1829 store <2 x ptr> %vec2, ptr addrspace(1) %out, align 4830 ret void831}832 833declare void @llvm.amdgcn.s.barrier() #1834 835attributes #0 = { nounwind }836attributes #1 = { convergent nounwind }837