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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -mattr=+relaxed-buffer-oob-mode -S -o - %s | FileCheck --check-prefixes=CHECK,CHECK-OOB-RELAXED %s3; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck --check-prefixes=CHECK,CHECK-OOB-STRICT %s4 5define amdgpu_kernel void @merge_v2i32_v2i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {6; CHECK-LABEL: define amdgpu_kernel void @merge_v2i32_v2i32(7; CHECK-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(1) [[B]], align 410; CHECK-NEXT: [[LD_C1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>11; CHECK-NEXT: [[LD_C_IDX_12:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>12; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr addrspace(1) [[A]], align 413; CHECK-NEXT: ret void14;15entry:16 %a.1 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %a, i64 117 %b.1 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %b, i64 118 19 %ld.c = load <2 x i32>, ptr addrspace(1) %b, align 420 %ld.c.idx.1 = load <2 x i32>, ptr addrspace(1) %b.1, align 421 22 store <2 x i32> zeroinitializer, ptr addrspace(1) %a, align 423 store <2 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 424 25 ret void26}27 28define amdgpu_kernel void @merge_v1i32_v1i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {29; CHECK-LABEL: define amdgpu_kernel void @merge_v1i32_v1i32(30; CHECK-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]]) #[[ATTR0]] {31; CHECK-NEXT: [[ENTRY:.*:]]32; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr addrspace(1) [[B]], align 433; CHECK-NEXT: [[LD_C1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <1 x i32> zeroinitializer34; CHECK-NEXT: [[LD_C_IDX_12:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <1 x i32> <i32 1>35; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr addrspace(1) [[A]], align 436; CHECK-NEXT: ret void37;38entry:39 %a.1 = getelementptr inbounds <1 x i32>, ptr addrspace(1) %a, i64 140 %b.1 = getelementptr inbounds <1 x i32>, ptr addrspace(1) %b, i64 141 42 %ld.c = load <1 x i32>, ptr addrspace(1) %b, align 443 %ld.c.idx.1 = load <1 x i32>, ptr addrspace(1) %b.1, align 444 45 store <1 x i32> zeroinitializer, ptr addrspace(1) %a, align 446 store <1 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 447 48 ret void49}50 51define amdgpu_kernel void @no_merge_v3i32_v3i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {52; CHECK-LABEL: define amdgpu_kernel void @no_merge_v3i32_v3i32(53; CHECK-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]]) #[[ATTR0]] {54; CHECK-NEXT: [[ENTRY:.*:]]55; CHECK-NEXT: [[A_1:%.*]] = getelementptr inbounds <3 x i32>, ptr addrspace(1) [[A]], i64 156; CHECK-NEXT: [[B_1:%.*]] = getelementptr inbounds <3 x i32>, ptr addrspace(1) [[B]], i64 157; CHECK-NEXT: [[LD_C:%.*]] = load <3 x i32>, ptr addrspace(1) [[B]], align 458; CHECK-NEXT: [[LD_C_IDX_1:%.*]] = load <3 x i32>, ptr addrspace(1) [[B_1]], align 459; CHECK-NEXT: store <3 x i32> zeroinitializer, ptr addrspace(1) [[A]], align 460; CHECK-NEXT: store <3 x i32> zeroinitializer, ptr addrspace(1) [[A_1]], align 461; CHECK-NEXT: ret void62;63entry:64 %a.1 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %a, i64 165 %b.1 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %b, i64 166 67 %ld.c = load <3 x i32>, ptr addrspace(1) %b, align 468 %ld.c.idx.1 = load <3 x i32>, ptr addrspace(1) %b.1, align 469 70 store <3 x i32> zeroinitializer, ptr addrspace(1) %a, align 471 store <3 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 472 73 ret void74}75 76define amdgpu_kernel void @merge_v2i16_v2i16(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {77; CHECK-LABEL: define amdgpu_kernel void @merge_v2i16_v2i16(78; CHECK-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]]) #[[ATTR0]] {79; CHECK-NEXT: [[ENTRY:.*:]]80; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr addrspace(1) [[B]], align 481; CHECK-NEXT: [[LD_C1:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>82; CHECK-NEXT: [[LD_C_IDX_12:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>83; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr addrspace(1) [[A]], align 484; CHECK-NEXT: ret void85;86entry:87 %a.1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %a, i64 188 %b.1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b, i64 189 90 %ld.c = load <2 x i16>, ptr addrspace(1) %b, align 491 %ld.c.idx.1 = load <2 x i16>, ptr addrspace(1) %b.1, align 492 93 store <2 x i16> zeroinitializer, ptr addrspace(1) %a, align 494 store <2 x i16> zeroinitializer, ptr addrspace(1) %a.1, align 495 96 ret void97}98 99define amdgpu_kernel void @merge_fat_ptrs(ptr addrspace(7) nocapture %a, ptr addrspace(7) nocapture readonly %b) #0 {100; CHECK-OOB-RELAXED-LABEL: define amdgpu_kernel void @merge_fat_ptrs(101; CHECK-OOB-RELAXED-SAME: ptr addrspace(7) captures(none) [[A:%.*]], ptr addrspace(7) readonly captures(none) [[B:%.*]]) #[[ATTR0]] {102; CHECK-OOB-RELAXED-NEXT: [[ENTRY:.*:]]103; CHECK-OOB-RELAXED-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr addrspace(7) [[B]], align 4104; CHECK-OOB-RELAXED-NEXT: [[LD_C1:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>105; CHECK-OOB-RELAXED-NEXT: [[LD_C_IDX_12:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>106; CHECK-OOB-RELAXED-NEXT: store <4 x i16> zeroinitializer, ptr addrspace(7) [[A]], align 4107; CHECK-OOB-RELAXED-NEXT: ret void108;109; CHECK-OOB-STRICT-LABEL: define amdgpu_kernel void @merge_fat_ptrs(110; CHECK-OOB-STRICT-SAME: ptr addrspace(7) captures(none) [[A:%.*]], ptr addrspace(7) readonly captures(none) [[B:%.*]]) #[[ATTR0]] {111; CHECK-OOB-STRICT-NEXT: [[ENTRY:.*:]]112; CHECK-OOB-STRICT-NEXT: [[A_1:%.*]] = getelementptr inbounds <2 x i16>, ptr addrspace(7) [[A]], i32 1113; CHECK-OOB-STRICT-NEXT: [[B_1:%.*]] = getelementptr inbounds <2 x i16>, ptr addrspace(7) [[B]], i32 1114; CHECK-OOB-STRICT-NEXT: [[LD_C:%.*]] = load <2 x i16>, ptr addrspace(7) [[B]], align 4115; CHECK-OOB-STRICT-NEXT: [[LD_C_IDX_1:%.*]] = load <2 x i16>, ptr addrspace(7) [[B_1]], align 4116; CHECK-OOB-STRICT-NEXT: store <2 x i16> zeroinitializer, ptr addrspace(7) [[A]], align 4117; CHECK-OOB-STRICT-NEXT: store <2 x i16> zeroinitializer, ptr addrspace(7) [[A_1]], align 4118; CHECK-OOB-STRICT-NEXT: ret void119;120entry:121 %a.1 = getelementptr inbounds <2 x i16>, ptr addrspace(7) %a, i32 1122 %b.1 = getelementptr inbounds <2 x i16>, ptr addrspace(7) %b, i32 1123 124 %ld.c = load <2 x i16>, ptr addrspace(7) %b, align 4125 %ld.c.idx.1 = load <2 x i16>, ptr addrspace(7) %b.1, align 4126 127 store <2 x i16> zeroinitializer, ptr addrspace(7) %a, align 4128 store <2 x i16> zeroinitializer, ptr addrspace(7) %a.1, align 4129 130 ret void131}132 133; Ideally this would be merged134define amdgpu_kernel void @merge_load_i32_v2i16(ptr addrspace(1) nocapture %a) #0 {135; CHECK-LABEL: define amdgpu_kernel void @merge_load_i32_v2i16(136; CHECK-SAME: ptr addrspace(1) captures(none) [[A:%.*]]) #[[ATTR0]] {137; CHECK-NEXT: [[ENTRY:.*:]]138; CHECK-NEXT: [[A_1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i32 1139; CHECK-NEXT: [[LD_0:%.*]] = load i32, ptr addrspace(1) [[A]], align 4140; CHECK-NEXT: [[LD_1:%.*]] = load <2 x i16>, ptr addrspace(1) [[A_1]], align 4141; CHECK-NEXT: ret void142;143entry:144 %a.1 = getelementptr inbounds i32, ptr addrspace(1) %a, i32 1145 146 %ld.0 = load i32, ptr addrspace(1) %a147 %ld.1 = load <2 x i16>, ptr addrspace(1) %a.1148 149 ret void150}151 152attributes #0 = { nounwind }153attributes #1 = { nounwind readnone }154