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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn--amdpal -passes=load-store-vectorizer -S -o - %s | FileCheck --check-prefix=OOB-STRICT %s3; RUN: opt -mtriple=amdgcn--amdpal -passes=load-store-vectorizer -mattr=+relaxed-buffer-oob-mode -S -o - %s | FileCheck --check-prefixes=OOB-RELAXED %s4 5; The test checks that relaxed-buffer-oob-mode allows merging loads even if the target load is not naturally aligned.6 7define amdgpu_kernel void @merge_align_4(ptr addrspace(7) captures(none) %p) #0 {8;9; OOB-STRICT-LABEL: define amdgpu_kernel void @merge_align_4(10; OOB-STRICT-SAME: ptr addrspace(7) captures(none) [[P:%.*]]) {11; OOB-STRICT-NEXT: [[ENTRY:.*:]]12; OOB-STRICT-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -813; OOB-STRICT-NEXT: [[LD_M8:%.*]] = load i32, ptr addrspace(7) [[GEP_M8]], align 414; OOB-STRICT-NEXT: [[GEP_M4:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -415; OOB-STRICT-NEXT: [[LD_M4:%.*]] = load i32, ptr addrspace(7) [[GEP_M4]], align 416; OOB-STRICT-NEXT: [[GEP_0:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 017; OOB-STRICT-NEXT: [[LD_0:%.*]] = load i32, ptr addrspace(7) [[GEP_0]], align 418; OOB-STRICT-NEXT: [[GEP_4:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i64 419; OOB-STRICT-NEXT: [[LD_4:%.*]] = load i32, ptr addrspace(7) [[GEP_4]], align 420; OOB-STRICT-NEXT: ret void21;22; OOB-RELAXED-LABEL: define amdgpu_kernel void @merge_align_4(23; OOB-RELAXED-SAME: ptr addrspace(7) captures(none) [[P:%.*]]) #[[ATTR0:[0-9]+]] {24; OOB-RELAXED-NEXT: [[ENTRY:.*:]]25; OOB-RELAXED-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -826; OOB-RELAXED-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 427; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 028; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 129; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 230; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 331; OOB-RELAXED-NEXT: ret void32;33entry:34 %gep_m8 = getelementptr i8, ptr addrspace(7) %p, i32 -835 %ld_m8 = load i32, ptr addrspace(7) %gep_m8, align 436 %gep_m4 = getelementptr i8, ptr addrspace(7) %p, i32 -437 %ld_m4 = load i32, ptr addrspace(7) %gep_m4, align 438 %gep_0 = getelementptr i8, ptr addrspace(7) %p, i32 039 %ld_0 = load i32, ptr addrspace(7) %gep_0, align 440 %gep_4 = getelementptr i8, ptr addrspace(7) %p, i64 441 %ld_4 = load i32, ptr addrspace(7) %gep_4, align 442 ret void43}44 45; The test checks that strict OOB mode (relaxed-buffer-oob-mode not set) allows merging loads if the target load is naturally aligned.46 47define amdgpu_kernel void @merge_align_16(ptr addrspace(7) captures(none) %p) #0 {48; OOB-STRICT-LABEL: define amdgpu_kernel void @merge_align_16(49; OOB-STRICT-SAME: ptr addrspace(7) captures(none) [[P:%.*]]) {50; OOB-STRICT-NEXT: [[ENTRY:.*:]]51; OOB-STRICT-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -852; OOB-STRICT-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 1653; OOB-STRICT-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 054; OOB-STRICT-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 155; OOB-STRICT-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 256; OOB-STRICT-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 357; OOB-STRICT-NEXT: ret void58;59; OOB-RELAXED-LABEL: define amdgpu_kernel void @merge_align_16(60; OOB-RELAXED-SAME: ptr addrspace(7) captures(none) [[P:%.*]]) #[[ATTR0]] {61; OOB-RELAXED-NEXT: [[ENTRY:.*:]]62; OOB-RELAXED-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -863; OOB-RELAXED-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 1664; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 065; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 166; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 267; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 368; OOB-RELAXED-NEXT: ret void69;70entry:71 %gep_m8 = getelementptr i8, ptr addrspace(7) %p, i32 -872 %ld_m8 = load i32, ptr addrspace(7) %gep_m8, align 1673 %gep_m4 = getelementptr i8, ptr addrspace(7) %p, i32 -474 %ld_m4 = load i32, ptr addrspace(7) %gep_m4, align 475 %gep_0 = getelementptr i8, ptr addrspace(7) %p, i32 076 %ld_0 = load i32, ptr addrspace(7) %gep_0, align 877 %gep_4 = getelementptr i8, ptr addrspace(7) %p, i64 478 %ld_4 = load i32, ptr addrspace(7) %gep_4, align 479 ret void80}81