85 lines · plain
1; RUN: opt -mtriple=nvptx64-nvidia-cuda -passes=load-store-vectorizer -S -o - %s | FileCheck %s2 3define void @ldg_f16(ptr nocapture align 16 %rd0) {4 %load1 = load <2 x half>, ptr %rd0, align 165 %p1 = fcmp ogt <2 x half> %load1, zeroinitializer6 %s1 = select <2 x i1> %p1, <2 x half> %load1, <2 x half> zeroinitializer7 store <2 x half> %s1, ptr %rd0, align 168 %in2 = getelementptr half, ptr %rd0, i64 29 %load2 = load <2 x half>, ptr %in2, align 410 %p2 = fcmp ogt <2 x half> %load2, zeroinitializer11 %s2 = select <2 x i1> %p2, <2 x half> %load2, <2 x half> zeroinitializer12 store <2 x half> %s2, ptr %in2, align 413 %in3 = getelementptr half, ptr %rd0, i64 414 %load3 = load <2 x half>, ptr %in3, align 415 %p3 = fcmp ogt <2 x half> %load3, zeroinitializer16 %s3 = select <2 x i1> %p3, <2 x half> %load3, <2 x half> zeroinitializer17 store <2 x half> %s3, ptr %in3, align 418 %in4 = getelementptr half, ptr %rd0, i64 619 %load4 = load <2 x half>, ptr %in4, align 420 %p4 = fcmp ogt <2 x half> %load4, zeroinitializer21 %s4 = select <2 x i1> %p4, <2 x half> %load4, <2 x half> zeroinitializer22 store <2 x half> %s4, ptr %in4, align 423 ret void24 25; CHECK-LABEL: @ldg_f1626; CHECK: %[[LD:.*]] = load <8 x half>, ptr27; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 0, i32 1>28; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 2, i32 3>29; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 4, i32 5>30; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 6, i32 7>31; CHECK: store <8 x half>32}33 34define void @no_nonpow2_vector(ptr nocapture align 16 %rd0) {35 %load1 = load <3 x half>, ptr %rd0, align 436 %p1 = fcmp ogt <3 x half> %load1, zeroinitializer37 %s1 = select <3 x i1> %p1, <3 x half> %load1, <3 x half> zeroinitializer38 store <3 x half> %s1, ptr %rd0, align 439 %in2 = getelementptr half, ptr %rd0, i64 340 %load2 = load <3 x half>, ptr %in2, align 441 %p2 = fcmp ogt <3 x half> %load2, zeroinitializer42 %s2 = select <3 x i1> %p2, <3 x half> %load2, <3 x half> zeroinitializer43 store <3 x half> %s2, ptr %in2, align 444 %in3 = getelementptr half, ptr %rd0, i64 645 %load3 = load <3 x half>, ptr %in3, align 446 %p3 = fcmp ogt <3 x half> %load3, zeroinitializer47 %s3 = select <3 x i1> %p3, <3 x half> %load3, <3 x half> zeroinitializer48 store <3 x half> %s3, ptr %in3, align 449 %in4 = getelementptr half, ptr %rd0, i64 950 %load4 = load <3 x half>, ptr %in4, align 451 %p4 = fcmp ogt <3 x half> %load4, zeroinitializer52 %s4 = select <3 x i1> %p4, <3 x half> %load4, <3 x half> zeroinitializer53 store <3 x half> %s4, ptr %in4, align 454 ret void55 56; CHECK-LABEL: @no_nonpow2_vector57; CHECK-NOT: shufflevector58}59 60define void @no_pointer_vector(ptr nocapture align 16 %rd0) {61 %load1 = load <2 x ptr>, ptr %rd0, align 462 %p1 = icmp ne <2 x ptr> %load1, zeroinitializer63 %s1 = select <2 x i1> %p1, <2 x ptr> %load1, <2 x ptr> zeroinitializer64 store <2 x ptr> %s1, ptr %rd0, align 465 %in2 = getelementptr ptr, ptr %rd0, i64 266 %load2 = load <2 x ptr>, ptr %in2, align 467 %p2 = icmp ne <2 x ptr> %load2, zeroinitializer68 %s2 = select <2 x i1> %p2, <2 x ptr> %load2, <2 x ptr> zeroinitializer69 store <2 x ptr> %s2, ptr %in2, align 470 %in3 = getelementptr ptr, ptr %rd0, i64 471 %load3 = load <2 x ptr>, ptr %in3, align 472 %p3 = icmp ne <2 x ptr> %load3, zeroinitializer73 %s3 = select <2 x i1> %p3, <2 x ptr> %load3, <2 x ptr> zeroinitializer74 store <2 x ptr> %s3, ptr %in3, align 475 %in4 = getelementptr ptr, ptr %rd0, i64 676 %load4 = load <2 x ptr>, ptr %in4, align 477 %p4 = icmp ne <2 x ptr> %load4, zeroinitializer78 %s4 = select <2 x i1> %p4, <2 x ptr> %load4, <2 x ptr> zeroinitializer79 store <2 x ptr> %s4, ptr %in4, align 480 ret void81 82; CHECK-LABEL: @no_pointer_vector83; CHECK-NOT: shufflevector84}85