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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -p loop-idiom -S %s | FileCheck %s3 4define void @fold_add_zext_to_sext(ptr %dst, i1 %start) {5; CHECK-LABEL: define void @fold_add_zext_to_sext(6; CHECK-SAME: ptr [[DST:%.*]], i1 [[START:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[START_EXT:%.*]] = zext i1 [[START]] to i329; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[START]] to i6410; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 211; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]]12; CHECK-NEXT: [[TMP4:%.*]] = shl nuw nsw i32 [[START_EXT]], 213; CHECK-NEXT: [[TMP2:%.*]] = sub i32 100, [[TMP4]]14; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6415; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[SCEVGEP]], i8 0, i64 [[TMP3]], i1 false)16; CHECK-NEXT: br label %[[LOOP:.*]]17; CHECK: [[LOOP]]:18; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START_EXT]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]19; CHECK-NEXT: [[IV_EXT:%.*]] = zext i32 [[IV]] to i6420; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_EXT]]21; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 122; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[IV]], 2423; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]]24; CHECK: [[EXIT]]:25; CHECK-NEXT: ret void26;27entry:28 %start.ext = zext i1 %start to i3229 br label %loop30 31loop:32 %iv = phi i32 [ %start.ext, %entry ], [ %iv.next, %loop ]33 %iv.ext = zext i32 %iv to i6434 %gep = getelementptr i32, ptr %dst, i64 %iv.ext35 store i32 0, ptr %gep, align 436 %iv.next = add i32 %iv, 137 %ec = icmp ult i32 %iv, 2438 br i1 %ec, label %loop, label %exit39 40exit:41 ret void42}43 44declare i16 @get()45 46define void @test_memset_size_can_use_info_from_guards(i32 %x, ptr %dst) {47; CHECK-LABEL: define void @test_memset_size_can_use_info_from_guards(48; CHECK-SAME: i32 [[X:%.*]], ptr [[DST:%.*]]) {49; CHECK-NEXT: [[ENTRY:.*]]:50; CHECK-NEXT: br label %[[LOOP1:.*]]51; CHECK: [[LOOP1_LOOPEXIT:.*]]:52; CHECK-NEXT: br label %[[LOOP1_BACKEDGE:.*]]53; CHECK: [[LOOP1]]:54; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[X]], %[[LOOP1_BACKEDGE]] ]55; CHECK-NEXT: [[L:%.*]] = call i16 @get()56; CHECK-NEXT: [[L_EXT:%.*]] = zext i16 [[L]] to i3257; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[L_EXT]], [[P]]58; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[SUB]], 159; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[SUB]], 260; CHECK-NEXT: br i1 [[EC]], label %[[LOOP1_BACKEDGE]], label %[[LOOP2_PREHEADER:.*]]61; CHECK: [[LOOP1_BACKEDGE]]:62; CHECK-NEXT: br label %[[LOOP1]]63; CHECK: [[LOOP2_PREHEADER]]:64; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[SUB]] to i6465; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 166; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 1)67; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[DST]], i8 0, i64 [[UMAX]], i1 false)68; CHECK-NEXT: br label %[[LOOP2:.*]]69; CHECK: [[LOOP2]]:70; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], %[[LOOP2]] ], [ 0, %[[LOOP2_PREHEADER]] ]71; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i32 [[IV_2]]72; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 173; CHECK-NEXT: [[EC_2:%.*]] = icmp ult i32 [[IV_2_NEXT]], [[SHR]]74; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP2]], label %[[LOOP1_LOOPEXIT]]75;76entry:77 br label %loop178 79loop1:80 %p = phi i32 [ 0, %entry ], [ %x, %loop1 ], [ %x, %loop2 ]81 %l = call i16 @get()82 %l.ext = zext i16 %l to i3283 %sub = sub i32 %l.ext, %p84 %shr = lshr i32 %sub, 185 %ec = icmp ult i32 %sub, 286 br i1 %ec, label %loop1, label %loop287 88loop2:89 %iv.2 = phi i32 [ 0, %loop1 ], [ %iv.2.next, %loop2 ]90 %gep.dst = getelementptr i8, ptr %dst, i32 %iv.291 store i8 0, ptr %gep.dst, align 192 %iv.2.next = add i32 %iv.2, 193 %ec.2 = icmp ult i32 %iv.2.next, %shr94 br i1 %ec.2, label %loop2, label %loop195}96