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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=loop-rotate < %s | FileCheck %s3 4define i64 @switch_multi_entry_known_entry() {5; CHECK-LABEL: @switch_multi_entry_known_entry(6; CHECK-NEXT: start:7; CHECK-NEXT: br label [[HEADER:%.*]]8; CHECK: header:9; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ 2, [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]10; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]11; CHECK-NEXT: switch i8 [[STATE]], label [[EXIT:%.*]] [12; CHECK-NEXT: i8 0, label [[LATCH]]13; CHECK-NEXT: i8 2, label [[LATCH]]14; CHECK-NEXT: ]15; CHECK: latch:16; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 99917; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i818; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 119; CHECK-NEXT: br label [[HEADER]]20; CHECK: exit:21; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ]22; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]23;24start:25 br label %header26 27header: ; preds = %latch, %start28 %state = phi i8 [ 2, %start ], [ %next_state, %latch ]29 %count = phi i64 [ 0, %start ], [ %inc, %latch ]30 switch i8 %state, label %exit [31 i8 0, label %latch32 i8 2, label %latch33 ]34 35latch: ; preds = %header, %header36 %cmp = icmp eq i64 %count, 99937 %next_state = zext i1 %cmp to i838 %inc = add i64 %count, 139 br label %header40 41exit: ; preds = %header42 ret i64 %count43}44 45define i64 @switch_multi_entry_unknown_entry(i8 %start_state) {46; CHECK-LABEL: @switch_multi_entry_unknown_entry(47; CHECK-NEXT: start:48; CHECK-NEXT: br label [[HEADER:%.*]]49; CHECK: header:50; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ [[START_STATE:%.*]], [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]51; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]52; CHECK-NEXT: switch i8 [[STATE]], label [[EXIT:%.*]] [53; CHECK-NEXT: i8 0, label [[LATCH]]54; CHECK-NEXT: i8 2, label [[LATCH]]55; CHECK-NEXT: ]56; CHECK: latch:57; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 99958; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i859; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 160; CHECK-NEXT: br label [[HEADER]]61; CHECK: exit:62; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ]63; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]64;65start:66 br label %header67 68header: ; preds = %latch, %start69 %state = phi i8 [ %start_state, %start ], [ %next_state, %latch ]70 %count = phi i64 [ 0, %start ], [ %inc, %latch ]71 switch i8 %state, label %exit [72 i8 0, label %latch73 i8 2, label %latch74 ]75 76latch: ; preds = %header, %header77 %cmp = icmp eq i64 %count, 99978 %next_state = zext i1 %cmp to i879 %inc = add i64 %count, 180 br label %header81 82exit: ; preds = %header83 ret i64 %count84}85 86define i64 @switch_multi_exit_known_entry() {87; CHECK-LABEL: @switch_multi_exit_known_entry(88; CHECK-NEXT: start:89; CHECK-NEXT: br label [[HEADER:%.*]]90; CHECK: header:91; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ 0, [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]92; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]93; CHECK-NEXT: switch i8 [[STATE]], label [[LATCH]] [94; CHECK-NEXT: i8 1, label [[EXIT:%.*]]95; CHECK-NEXT: i8 2, label [[EXIT]]96; CHECK-NEXT: ]97; CHECK: latch:98; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 99999; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8100; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1101; CHECK-NEXT: br label [[HEADER]]102; CHECK: exit:103; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ], [ [[COUNT]], [[HEADER]] ]104; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]105;106start:107 br label %header108 109header: ; preds = %latch, %start110 %state = phi i8 [ 0, %start ], [ %next_state, %latch ]111 %count = phi i64 [ 0, %start ], [ %inc, %latch ]112 switch i8 %state, label %latch [113 i8 1, label %exit114 i8 2, label %exit115 ]116 117latch: ; preds = %header, %header118 %cmp = icmp eq i64 %count, 999119 %next_state = zext i1 %cmp to i8120 %inc = add i64 %count, 1121 br label %header122 123exit: ; preds = %header124 ret i64 %count125}126 127define i64 @switch_multi_exit_unknown_entry(i8 %start_state) {128; CHECK-LABEL: @switch_multi_exit_unknown_entry(129; CHECK-NEXT: start:130; CHECK-NEXT: br label [[HEADER:%.*]]131; CHECK: header:132; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ [[START_STATE:%.*]], [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]133; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]134; CHECK-NEXT: switch i8 [[STATE]], label [[LATCH]] [135; CHECK-NEXT: i8 1, label [[EXIT:%.*]]136; CHECK-NEXT: i8 2, label [[EXIT]]137; CHECK-NEXT: ]138; CHECK: latch:139; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 999140; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8141; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1142; CHECK-NEXT: br label [[HEADER]]143; CHECK: exit:144; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ], [ [[COUNT]], [[HEADER]] ]145; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]146;147start:148 br label %header149 150header: ; preds = %latch, %start151 %state = phi i8 [ %start_state, %start ], [ %next_state, %latch ]152 %count = phi i64 [ 0, %start ], [ %inc, %latch ]153 switch i8 %state, label %latch [154 i8 1, label %exit155 i8 2, label %exit156 ]157 158latch: ; preds = %header, %header159 %cmp = icmp eq i64 %count, 999160 %next_state = zext i1 %cmp to i8161 %inc = add i64 %count, 1162 br label %header163 164exit: ; preds = %header165 ret i64 %count166}167