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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -passes='loop-mssa(loop-rotate,licm),instcombine,indvars,loop-unroll' -S %s | FileCheck %s3;4; PR18361: ScalarEvolution::getAddRecExpr():5; Assertion `isLoopInvariant(Operands[i],...6;7; After a series of loop optimizations, SCEV's LoopDispositions grow stale.8; In particular, LoopSimplify hoists %cmp4, resulting in this SCEV for %add:9; {(zext i1 %cmp4 to i32),+,1}<nw><%for.cond1.preheader>10;11; When recomputing the SCEV for %ashr, we truncate the operands to get:12; (zext i1 %cmp4 to i16)13;14; This SCEV was never mapped to a value so never invalidated. It's15; loop disposition is still marked as non-loop-invariant, which is16; inconsistent with the AddRec.17 18target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"19target triple = "x86_64-apple-macosx"20 21@d = common global i32 0, align 422@a = common global i32 0, align 423@c = common global i32 0, align 424@b = common global i32 0, align 425 26; Check that the def-use chain that leads to the bad SCEV is still27; there.28define void @foo() {29; CHECK-LABEL: define void @foo() {30; CHECK-NEXT: entry:31; CHECK-NEXT: store i32 0, ptr @d, align 432; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @c, align 433; CHECK-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]34; CHECK: for.cond1.preheader:35; CHECK-NEXT: br label [[FOR_BODY3:%.*]]36; CHECK: for.body3:37; CHECK-NEXT: store i32 1, ptr @a, align 438; CHECK-NEXT: store i32 1, ptr @d, align 439; CHECK-NEXT: [[CMP4_LE_LE_INV:%.*]] = icmp sgt i32 [[TMP0]], 040; CHECK-NEXT: br i1 [[CMP4_LE_LE_INV]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]41; CHECK: if.then:42; CHECK-NEXT: store i32 0, ptr @b, align 443; CHECK-NEXT: br label [[IF_END]]44; CHECK: if.end:45; CHECK-NEXT: ret void46;47entry:48 br label %for.cond49 50for.cond: ; preds = %for.inc7, %entry51 %storemerge = phi i32 [ 0, %entry ], [ %inc8, %for.inc7 ]52 %f.0 = phi i32 [ undef, %entry ], [ %f.1, %for.inc7 ]53 store i32 %storemerge, ptr @d, align 454 %cmp = icmp slt i32 %storemerge, 155 br i1 %cmp, label %for.cond1, label %for.end956 57for.cond1: ; preds = %for.cond, %for.body358 %storemerge1 = phi i32 [ %inc, %for.body3 ], [ 0, %for.cond ]59 %f.1 = phi i32 [ %xor, %for.body3 ], [ %f.0, %for.cond ]60 store i32 %storemerge1, ptr @a, align 461 %cmp2 = icmp slt i32 %storemerge1, 162 br i1 %cmp2, label %for.body3, label %for.inc763 64for.body3: ; preds = %for.cond165 %0 = load i32, ptr @c, align 466 %cmp4 = icmp sge i32 %storemerge1, %067 %conv = zext i1 %cmp4 to i3268 %1 = load i32, ptr @d, align 469 %add = add nsw i32 %conv, %170 %sext = shl i32 %add, 1671 %conv6 = ashr exact i32 %sext, 1672 %xor = xor i32 %conv6, 173 %inc = add nsw i32 %storemerge1, 174 br label %for.cond175 76for.inc7: ; preds = %for.cond177 %2 = load i32, ptr @d, align 478 %inc8 = add nsw i32 %2, 179 br label %for.cond80 81for.end9: ; preds = %for.cond82 %cmp10 = icmp sgt i32 %f.0, 083 br i1 %cmp10, label %if.then, label %if.end84 85if.then: ; preds = %for.end986 store i32 0, ptr @b, align 487 br label %if.end88 89if.end: ; preds = %if.then, %for.end990 ret void91}92