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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -verify-scev -passes='loop(require<iv-users>),loop-mssa(loop-simplifycfg)' -S %s | FileCheck --check-prefixes=CHECK,IVUSERS %s3; RUN: opt -verify-scev -passes="indvars,loop-simplifycfg" -S %s | FileCheck --check-prefixes=CHECK,INDVARS %s4 5target datalayout = "p:16:16-n16:32"6 7define void @test_pr58179_remove_dead_block_from_loop() {8; CHECK-LABEL: @test_pr58179_remove_dead_block_from_loop(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[A:%.*]] = alloca [10 x i64], align 111; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]12; CHECK: outer.header:13; CHECK-NEXT: br label [[OUTER_HEADER]]14;15entry:16 %a = alloca [10 x i64], align 117 br label %outer.header18 19outer.header:20 br i1 false, label %inner, label %outer.header21 22inner:23 %iv = phi i16 [ 0, %outer.header ], [ %iv.next, %inner ]24 %gep = getelementptr inbounds [10 x i64], ptr %a, i32 0, i16 %iv25 store i64 0, ptr %gep26 %iv.next = add nsw i16 %iv, 127 br i1 false, label %inner, label %outer.header28}29 30define void @test_remove_instrs_in_exit_block() {31; IVUSERS-LABEL: @test_remove_instrs_in_exit_block(32; IVUSERS-NEXT: entry:33; IVUSERS-NEXT: [[A:%.*]] = alloca [10 x i64], align 134; IVUSERS-NEXT: br label [[OUTER_HEADER:%.*]]35; IVUSERS: outer.header:36; IVUSERS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]37; IVUSERS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [38; IVUSERS-NEXT: i32 1, label [[OUTER_LATCH]]39; IVUSERS-NEXT: ]40; IVUSERS: outer.header.split:41; IVUSERS-NEXT: br label [[INNER:%.*]]42; IVUSERS: inner:43; IVUSERS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]44; IVUSERS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]45; IVUSERS-NEXT: store i64 0, ptr [[GEP]], align 446; IVUSERS-NEXT: [[L:%.*]] = call i16 @get()47; IVUSERS-NEXT: [[IV_NEXT]] = add nsw i16 [[IV]], 148; IVUSERS-NEXT: br label [[INNER]]49; IVUSERS: outer.latch:50; IVUSERS-NEXT: [[OUTER_IV_NEXT]] = add nsw i16 [[OUTER_IV]], 151; IVUSERS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]52; IVUSERS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]53; IVUSERS: exit:54; IVUSERS-NEXT: ret void55;56; INDVARS-LABEL: @test_remove_instrs_in_exit_block(57; INDVARS-NEXT: entry:58; INDVARS-NEXT: [[A:%.*]] = alloca [10 x i64], align 159; INDVARS-NEXT: br label [[OUTER_HEADER:%.*]]60; INDVARS: outer.header:61; INDVARS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]62; INDVARS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [63; INDVARS-NEXT: i32 1, label [[OUTER_LATCH]]64; INDVARS-NEXT: ]65; INDVARS: outer.header.split:66; INDVARS-NEXT: br label [[INNER:%.*]]67; INDVARS: inner:68; INDVARS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]69; INDVARS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]70; INDVARS-NEXT: store i64 0, ptr [[GEP]], align 471; INDVARS-NEXT: [[L:%.*]] = call i16 @get()72; INDVARS-NEXT: [[IV_NEXT]] = add nuw nsw i16 [[IV]], 173; INDVARS-NEXT: br label [[INNER]]74; INDVARS: outer.latch:75; INDVARS-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i16 [[OUTER_IV]], 176; INDVARS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]77; INDVARS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]78; INDVARS: exit:79; INDVARS-NEXT: ret void80;81entry:82 %a = alloca [10 x i64], align 183 br label %outer.header84 85outer.header:86 %outer.iv = phi i16 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]87 br label %inner88 89inner:90 %iv = phi i16 [ 0, %outer.header ], [ %iv.next, %inner ]91 %gep = getelementptr inbounds [10 x i64], ptr %a, i32 0, i16 %iv92 store i64 0, ptr %gep93 %l = call i16 @get()94 %iv.next = add nsw i16 %iv, 195 br i1 true, label %inner, label %outer.latch96 97outer.latch:98 %l.lcssa = phi i16 [ %l, %inner ]99 %outer.iv.next = add nsw i16 %outer.iv, 1100 %cmp.2 = icmp eq i16 %l.lcssa, %outer.iv101 br i1 %cmp.2, label %outer.header, label %exit102 103exit:104 ret void105}106 107declare i16 @get()108 109define i32 @test_pr58489(i32 %a) {110; CHECK-LABEL: @test_pr58489(111; CHECK-NEXT: entry:112; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[A:%.*]], -23113; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])114; CHECK-NEXT: switch i32 0, label [[ENTRY_SPLIT:%.*]] [115; CHECK-NEXT: i32 1, label [[EXIT:%.*]]116; CHECK-NEXT: ]117; CHECK: entry.split:118; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]119; CHECK: loop.header:120; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[SHIFT:%.*]], [[LOOP_HEADER]] ]121; CHECK-NEXT: [[C_2:%.*]] = icmp ne i32 [[P]], 0122; CHECK-NEXT: [[C_2_EXT:%.*]] = zext i1 [[C_2]] to i16123; CHECK-NEXT: call void @use(i16 [[C_2_EXT]])124; CHECK-NEXT: [[SHIFT]] = ashr exact i32 [[A]], 16125; CHECK-NEXT: br label [[LOOP_HEADER]]126; CHECK: exit:127; CHECK-NEXT: ret i32 poison128;129entry:130 %c.1 = icmp slt i32 %a, -23131 call void @llvm.assume(i1 %c.1)132 br label %loop.header133 134loop.header:135 %p = phi i32 [ 0, %entry ], [ %shift, %loop.latch ]136 br label %loop.latch137 138loop.latch:139 %c.2 = icmp ne i32 %p, 0140 %c.2.ext = zext i1 %c.2 to i16141 call void @use(i16 %c.2.ext)142 %shift = ashr exact i32 %a, 16143 switch i32 50, label %exit [144 i32 50, label %loop.header145 ]146 147exit:148 %shift.lcssa = phi i32 [ %shift, %loop.latch ]149 ret i32 %shift.lcssa150}151 152declare void @llvm.assume(i1 noundef) #0153 154declare void @use(i16)155