89 lines · plain
1; RUN: opt -loop-reduce -S < %s | FileCheck %s2;3; <rdar://10619599> "SelectionDAGBuilder shouldn't visit PHI nodes!" assert.4; <rdar://10655343> SCEVExpander segfault on simple test case5 6target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32"7target triple = "i386-apple-darwin"8 9; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*.10; This involves a nested AddRec, the outer AddRec's loop invariant components11; cannot find a preheader, so they should be expanded in the loop header12; (bb7.lr.ph.us) below the existing phi i.12.us.13; Currently, LSR won't kick in on such loops.14; CHECK-LABEL: @nopreheader(15; CHECK: bb7.us:16; CHECK-NOT: phi ptr17; CHECK: %j.01.us = phi i3218; CHECK-NOT: phi ptr19define void @nopreheader(ptr nocapture %a, i32 %n) nounwind {20entry:21 %0 = sdiv i32 %n, undef22 indirectbr ptr undef, [label %bb10.preheader]23 24bb10.preheader: ; preds = %bb425 indirectbr ptr undef, [label %bb8.preheader.lr.ph, label %return]26 27bb8.preheader.lr.ph: ; preds = %bb10.preheader28 indirectbr ptr null, [label %bb7.lr.ph.us, label %bb9]29 30bb7.lr.ph.us: ; preds = %bb9.us, %bb8.preheader.lr.ph31 %i.12.us = phi i32 [ %2, %bb9.us ], [ 0, %bb8.preheader.lr.ph ]32 %tmp30 = mul i32 %0, %i.12.us33 indirectbr ptr undef, [label %bb7.us]34 35bb7.us: ; preds = %bb7.lr.ph.us, %bb7.us36 %j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ]37 %tmp31 = add i32 %tmp30, %j.01.us38 %scevgep9 = getelementptr float, ptr %a, i32 %tmp3139 store float undef, ptr %scevgep9, align 140 %1 = add nsw i32 %j.01.us, 141 indirectbr ptr undef, [label %bb9.us, label %bb7.us]42 43bb9.us: ; preds = %bb7.us44 %2 = add nsw i32 %i.12.us, 145 indirectbr ptr undef, [label %bb7.lr.ph.us, label %return]46 47bb9: ; preds = %bb9, %bb8.preheader.lr.ph48 indirectbr ptr undef, [label %bb9, label %return]49 50return: ; preds = %bb9, %bb9.us, %bb10.preheader51 ret void52}53 54; In this case, SCEVExpander simply cannot materialize the AddRecExpr55; that LSR picks. We must detect that %bb8.preheader does not have a56; preheader and avoid performing LSR on %bb7.57; CHECK-LABEL: @nopreheader2(58; CHECK: bb7:59; CHECK: %indvar = phi i3260define fastcc void @nopreheader2(ptr nocapture %Array2) nounwind {61entry:62 indirectbr ptr undef, [label %bb]63 64bb: ; preds = %bb, %entry65 indirectbr ptr undef, [label %bb3, label %bb]66 67bb3: ; preds = %bb3, %bb68 indirectbr ptr undef, [label %bb8.preheader, label %bb3]69 70bb8.preheader: ; preds = %bb9, %bb371 %indvar5 = phi i32 [ %indvar.next6, %bb9 ], [ 0, %bb3 ]72 %tmp26 = add i32 %indvar5, 1373 indirectbr ptr null, [label %bb7]74 75bb7: ; preds = %bb8.preheader, %bb776 %indvar = phi i32 [ 0, %bb8.preheader ], [ %indvar.next, %bb7 ]77 %scevgep = getelementptr [200 x i32], ptr %Array2, i32 %tmp26, i32 %indvar78 store i32 undef, ptr %scevgep, align 479 %indvar.next = add i32 %indvar, 180 indirectbr ptr undef, [label %bb9, label %bb7]81 82bb9: ; preds = %bb783 %indvar.next6 = add i32 %indvar5, 184 indirectbr ptr undef, [label %return, label %bb8.preheader]85 86return: ; preds = %bb987 ret void88}89