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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s3 4; TODO: ldp don't support r+r, we need to avoid lsr optimize this pattern5define void @convolution(ptr %src0, ptr %src1, i64 %stride_xm, i64 %stride_xp, ptr %dst, i32 %w) {6; CHECK-LABEL: convolution:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: mov x8, xzr9; CHECK-NEXT: add x9, x1, x310; CHECK-NEXT: add x10, x1, x211; CHECK-NEXT: add x11, x0, x212; CHECK-NEXT: add x12, x0, x313; CHECK-NEXT: .LBB0_1: // %do.body14; CHECK-NEXT: // =>This Inner Loop Header: Depth=115; CHECK-NEXT: add x13, x1, x816; CHECK-NEXT: add x14, x0, x817; CHECK-NEXT: ldr q0, [x11, x8]18; CHECK-NEXT: ldp q2, q3, [x14]19; CHECK-NEXT: ldr q1, [x12, x8]20; CHECK-NEXT: ldp q6, q7, [x13]21; CHECK-NEXT: subs w5, w5, #122; CHECK-NEXT: ldr q4, [x10, x8]23; CHECK-NEXT: ldr q5, [x9, x8]24; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s25; CHECK-NEXT: fadd v1.4s, v2.4s, v3.4s26; CHECK-NEXT: add x8, x8, #3227; CHECK-NEXT: fadd v2.4s, v4.4s, v5.4s28; CHECK-NEXT: fadd v3.4s, v6.4s, v7.4s29; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s30; CHECK-NEXT: fadd v1.4s, v2.4s, v3.4s31; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s32; CHECK-NEXT: str q0, [x4], #1633; CHECK-NEXT: b.ne .LBB0_134; CHECK-NEXT: // %bb.2: // %do.end35; CHECK-NEXT: ret36entry:37 br label %do.body38 39do.body:40 %dst.addr.0 = phi ptr [ %dst, %entry ], [ %incdec.ptr, %do.body ]41 %src1.addr.0 = phi ptr [ %src1, %entry ], [ %incdec.ptr2.i7, %do.body ]42 %src0.addr.0 = phi ptr [ %src0, %entry ], [ %incdec.ptr2.i, %do.body ]43 %w.addr.0 = phi i32 [ %w, %entry ], [ %dec, %do.body ]44 %add.ptr.i = getelementptr inbounds i8, ptr %src0.addr.0, i64 %stride_xm45 %0 = load <4 x float>, ptr %add.ptr.i, align 1646 %add.ptr1.i = getelementptr inbounds i8, ptr %src0.addr.0, i64 %stride_xp47 %1 = load <4 x float>, ptr %add.ptr1.i, align 1648 %incdec.ptr.i = getelementptr inbounds <4 x float>, ptr %src0.addr.0, i64 149 %2 = load <4 x float>, ptr %src0.addr.0, align 1650 %incdec.ptr2.i = getelementptr inbounds <4 x float>, ptr %src0.addr.0, i64 251 %3 = load <4 x float>, ptr %incdec.ptr.i, align 1652 %add.i = fadd <4 x float> %0, %153 %add3.i = fadd <4 x float> %2, %354 %add4.i = fadd <4 x float> %add.i, %add3.i55 %add.ptr.i4 = getelementptr inbounds i8, ptr %src1.addr.0, i64 %stride_xm56 %4 = load <4 x float>, ptr %add.ptr.i4, align 1657 %add.ptr1.i5 = getelementptr inbounds i8, ptr %src1.addr.0, i64 %stride_xp58 %5 = load <4 x float>, ptr %add.ptr1.i5, align 1659 %incdec.ptr.i6 = getelementptr inbounds <4 x float>, ptr %src1.addr.0, i64 160 %6 = load <4 x float>, ptr %src1.addr.0, align 1661 %incdec.ptr2.i7 = getelementptr inbounds <4 x float>, ptr %src1.addr.0, i64 262 %7 = load <4 x float>, ptr %incdec.ptr.i6, align 1663 %add.i8 = fadd <4 x float> %4, %564 %add3.i9 = fadd <4 x float> %6, %765 %add4.i10 = fadd <4 x float> %add.i8, %add3.i966 %add = fadd <4 x float> %add4.i, %add4.i1067 %incdec.ptr = getelementptr inbounds <4 x float>, ptr %dst.addr.0, i64 168 store <4 x float> %add, ptr %dst.addr.0, align 1669 %dec = add nsw i32 %w.addr.0, -170 %tobool.not = icmp eq i32 %dec, 071 br i1 %tobool.not, label %do.end, label %do.body72 73do.end:74 ret void75}76