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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -lsr-preferred-addressing-mode=preindexed %s -o - | FileCheck %s3 4; In LSR for constant offsets and steps, we can generate pre-inc5; accesses by having the offset equal the step and generate a reuse6; formula. However, there are cases where the step, results in an7; illegal addressing mode.8 9; In this test, we set the preferred addressing mode to be preindexed,10; in order to test a scenario where the step results in an illegal11; addressing mode and because of that it should not generate a reuse formula.12 13; This test was created in order to reproduce a bug that was observed14; when building a bootstrap build on an AArch64 machine, where the15; preferred addresing mode is preindexed.16 17 18%"Type" = type <{[166 x [338 x i8]]}>19define void @test_lsr_pre_inc_offset_check(ptr %p) {20; CHECK-LABEL: test_lsr_pre_inc_offset_check:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: mov w8, #16523; CHECK-NEXT: add x9, x0, #33924; CHECK-NEXT: mov w10, #225; CHECK-NEXT: .LBB0_1: // %main26; CHECK-NEXT: // =>This Inner Loop Header: Depth=127; CHECK-NEXT: str wzr, [x9]28; CHECK-NEXT: subs x8, x8, #129; CHECK-NEXT: strb w10, [x9, #1]30; CHECK-NEXT: add x9, x9, #33831; CHECK-NEXT: b.ne .LBB0_132; CHECK-NEXT: // %bb.2: // %exit33; CHECK-NEXT: ret34entry:35 br label %main36exit:37 ret void38if.then:39 %arrayidx.i = getelementptr inbounds %"Type", ptr %p, i64 0, i32 0, i64 %indvars, i64 140 store i32 0, ptr %arrayidx.i, align 141 br label %if.end42if.end:43 %arrayidx.p = getelementptr inbounds %"Type", ptr %p, i64 0, i32 0, i64 %indvars, i64 244 store i8 2, ptr %arrayidx.p, align 145 %indvars.iv.next = add nuw nsw i64 %indvars, 146 %add.i = add nuw i8 %begin, 147 %cmp.i.not = icmp eq i64 %indvars.iv.next, 16648 br i1 %cmp.i.not, label %exit, label %main49main:50 %begin = phi i8 [ 1, %entry ], [ %add.i, %if.end ]51 %indvars = phi i64 [ 1, %entry ], [ %indvars.iv.next, %if.end ]52 br label %if.then53}54