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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=aarch64-none-elf -loop-reduce -lsr-preferred-addressing-mode=all < %s | FileCheck %s3 4define i32 @postindex_loop(ptr %p, i64 %n) {5; CHECK-LABEL: define i32 @postindex_loop(6; CHECK-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: br label %[[FOR_BODY:.*]]9; CHECK: [[FOR_BODY]]:10; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_BODY]] ], [ [[P]], %[[ENTRY]] ]11; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[N]], %[[ENTRY]] ]12; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ]13; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[LSR_IV1]], align 414; CHECK-NEXT: [[ADD]] = add i32 [[RET]], [[VAL]]15; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -116; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV1]], i64 417; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 018; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[FOR_BODY]]19; CHECK: [[EXIT]]:20; CHECK-NEXT: ret i32 [[ADD]]21;22entry:23 br label %for.body24 25for.body:26 %idx = phi i64 [ %idx.next, %for.body ], [ 0, %entry ]27 %ret = phi i32 [ %add, %for.body ], [ 0, %entry ]28 %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx29 %val = load i32, ptr %arrayidx, align 430 %add = add i32 %ret, %val31 %idx.next = add nuw nsw i64 %idx, 132 %exitcond = icmp eq i64 %idx.next, %n33 br i1 %exitcond, label %exit, label %for.body34 35exit:36 ret i32 %add37}38 39; Preindex saves a setup instruction compared to postindex40; FIXME: We currently don't recognize that preindex is possible here41define i32 @preindex_loop(ptr %p, i64 %n) {42; CHECK-LABEL: define i32 @preindex_loop(43; CHECK-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) {44; CHECK-NEXT: [[ENTRY:.*]]:45; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr nuw i8, ptr [[P]], i64 446; CHECK-NEXT: br label %[[FOR_BODY:.*]]47; CHECK: [[FOR_BODY]]:48; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], %[[FOR_BODY]] ], [ [[SCEVGEP]], %[[ENTRY]] ]49; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[N]], %[[ENTRY]] ]50; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ]51; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[LSR_IV1]], align 452; CHECK-NEXT: [[ADD]] = add i32 [[RET]], [[VAL]]53; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -154; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 455; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 056; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[FOR_BODY]]57; CHECK: [[EXIT]]:58; CHECK-NEXT: ret i32 [[ADD]]59;60entry:61 br label %for.body62 63for.body:64 %idx = phi i64 [ %idx.next, %for.body ], [ 0, %entry ]65 %ret = phi i32 [ %add, %for.body ], [ 0, %entry ]66 %idx.next = add nuw nsw i64 %idx, 167 %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.next68 %val = load i32, ptr %arrayidx, align 469 %add = add i32 %ret, %val70 %exitcond = icmp eq i64 %idx.next, %n71 br i1 %exitcond, label %exit, label %for.body72 73exit:74 ret i32 %add75}76 77; We should use offset addressing here as postindex uses an extra register.78; FIXME: We currently use postindex as we don't realize the load of val2 is also79; a use of p that needs it to be live in the loop.80define i64 @offset_loop(ptr %p, i64 %n) {81; CHECK-LABEL: define i64 @offset_loop(82; CHECK-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) {83; CHECK-NEXT: [[ENTRY:.*]]:84; CHECK-NEXT: br label %[[FOR_BODY:.*]]85; CHECK: [[FOR_BODY]]:86; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_BODY]] ], [ [[P]], %[[ENTRY]] ]87; CHECK-NEXT: [[RET:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]88; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IDX_NEXT:%.*]], %[[FOR_BODY]] ]89; CHECK-NEXT: [[VAL1:%.*]] = load i64, ptr [[LSR_IV]], align 490; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i64, ptr [[P]], i64 [[VAL1]]91; CHECK-NEXT: [[VAL2:%.*]] = load i64, ptr [[ARRAYIDX2]], align 492; CHECK-NEXT: [[ADD]] = add i64 [[VAL2]], [[RET]]93; CHECK-NEXT: [[IDX_NEXT]] = add nuw nsw i64 [[IDX]], 194; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 895; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IDX_NEXT]], [[VAL1]]96; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_END:.*]], label %[[FOR_BODY]]97; CHECK: [[FOR_END]]:98; CHECK-NEXT: ret i64 [[ADD]]99;100entry:101 br label %for.body102 103for.body:104 %ret = phi i64 [ 0, %entry ], [ %add, %for.body ]105 %idx = phi i64 [ 0, %entry ], [ %idx.next, %for.body ]106 %arrayidx1 = getelementptr inbounds nuw i64, ptr %p, i64 %idx107 %val1 = load i64, ptr %arrayidx1, align 4108 %arrayidx2 = getelementptr inbounds nuw i64, ptr %p, i64 %val1109 %val2 = load i64, ptr %arrayidx2, align 4110 %add = add i64 %val2, %ret111 %idx.next = add nuw nsw i64 %idx, 1112 %cmp = icmp eq i64 %idx.next, %val1113 br i1 %cmp, label %for.end, label %for.body114 115for.end:116 ret i64 %add117}118 119; We can't use postindex addressing on the conditional load of qval and can't120; convert the loop condition to a compare with zero, so we should instead use121; offset addressing.122define i32 @conditional_load(ptr %p, ptr %q, ptr %n) {123; CHECK-LABEL: define i32 @conditional_load(124; CHECK-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], ptr [[N:%.*]]) {125; CHECK-NEXT: [[ENTRY:.*]]:126; CHECK-NEXT: br label %[[FOR_BODY:.*]]127; CHECK: [[FOR_BODY]]:128; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], %[[FOR_INC:.*]] ], [ [[P]], %[[ENTRY]] ]129; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ [[IDX_NEXT:%.*]], %[[FOR_INC]] ], [ 0, %[[ENTRY]] ]130; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[RET_NEXT:%.*]], %[[FOR_INC]] ], [ 0, %[[ENTRY]] ]131; CHECK-NEXT: [[PVAL:%.*]] = load i32, ptr [[LSR_IV1]], align 4132; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[PVAL]], 0133; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4134; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[FOR_INC]], label %[[IF_THEN:.*]]135; CHECK: [[IF_THEN]]:136; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IDX]], 2137; CHECK-NEXT: [[LSR_IV:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP0]]138; CHECK-NEXT: [[QVAL:%.*]] = load i32, ptr [[LSR_IV]], align 4139; CHECK-NEXT: [[ADD:%.*]] = add i32 [[RET]], [[QVAL]]140; CHECK-NEXT: br label %[[FOR_INC]]141; CHECK: [[FOR_INC]]:142; CHECK-NEXT: [[RET_NEXT]] = phi i32 [ [[ADD]], %[[IF_THEN]] ], [ [[RET]], %[[FOR_BODY]] ]143; CHECK-NEXT: [[IDX_NEXT]] = add nuw nsw i64 [[IDX]], 1144; CHECK-NEXT: [[NVAL:%.*]] = load volatile i64, ptr [[N]], align 8145; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[IDX_NEXT]], [[NVAL]]146; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT:.*]]147; CHECK: [[EXIT]]:148; CHECK-NEXT: ret i32 [[RET_NEXT]]149;150entry:151 br label %for.body152 153for.body:154 %idx = phi i64 [ %idx.next, %for.inc ], [ 0, %entry ]155 %ret = phi i32 [ %ret.next, %for.inc ], [ 0, %entry ]156 %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx157 %pval = load i32, ptr %arrayidx, align 4158 %tobool.not = icmp eq i32 %pval, 0159 br i1 %tobool.not, label %for.inc, label %if.then160 161if.then:162 %arrayidx1 = getelementptr inbounds nuw i32, ptr %q, i64 %idx163 %qval = load i32, ptr %arrayidx1, align 4164 %add = add i32 %ret, %qval165 br label %for.inc166 167for.inc:168 %ret.next = phi i32 [ %add, %if.then ], [ %ret, %for.body ]169 %idx.next = add nuw nsw i64 %idx, 1170 %nval = load volatile i64, ptr %n, align 8171 %cmp = icmp slt i64 %idx.next, %nval172 br i1 %cmp, label %for.body, label %exit173 174exit:175 ret i32 %ret.next176}177 178; We can use postindex addressing for both loads here, even though the second179; may not be executed on every loop iteration.180define i32 @early_exit_load(ptr %p, ptr %q, ptr %n) {181; CHECK-LABEL: define i32 @early_exit_load(182; CHECK-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], ptr [[N:%.*]]) {183; CHECK-NEXT: [[ENTRY:.*]]:184; CHECK-NEXT: br label %[[FOR_BODY:.*]]185; CHECK: [[FOR_BODY]]:186; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], %[[FOR_INC:.*]] ], [ [[P]], %[[ENTRY]] ]187; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_INC]] ], [ [[Q]], %[[ENTRY]] ]188; CHECK-NEXT: [[RET_PHI:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_INC]] ], [ 0, %[[ENTRY]] ]189; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ [[IDX_NEXT:%.*]], %[[FOR_INC]] ], [ 0, %[[ENTRY]] ]190; CHECK-NEXT: [[PVAL:%.*]] = load i32, ptr [[LSR_IV1]], align 4191; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[PVAL]], 0192; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4193; CHECK-NEXT: br i1 [[CMP1]], label %[[FOR_INC]], label %[[EXIT:.*]]194; CHECK: [[FOR_INC]]:195; CHECK-NEXT: [[QVAL:%.*]] = load i32, ptr [[LSR_IV]], align 4196; CHECK-NEXT: [[ADD]] = add nsw i32 [[QVAL]], [[RET_PHI]]197; CHECK-NEXT: [[IDX_NEXT]] = add nuw nsw i64 [[IDX]], 1198; CHECK-NEXT: [[NVAL:%.*]] = load volatile i64, ptr [[N]], align 8199; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 4200; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i64 [[IDX_NEXT]], [[NVAL]]201; CHECK-NEXT: br i1 [[CMP2]], label %[[FOR_BODY]], label %[[EXIT]]202; CHECK: [[EXIT]]:203; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[RET_PHI]], %[[FOR_BODY]] ], [ [[ADD]], %[[FOR_INC]] ]204; CHECK-NEXT: ret i32 [[RET]]205;206entry:207 br label %for.body208 209for.body:210 %ret.phi = phi i32 [ %add, %for.inc ], [ 0, %entry ]211 %idx = phi i64 [ %idx.next, %for.inc ], [ 0, %entry ]212 %paddr = getelementptr inbounds nuw i32, ptr %p, i64 %idx213 %pval = load i32, ptr %paddr, align 4214 %cmp1 = icmp eq i32 %pval, 0215 br i1 %cmp1, label %for.inc, label %exit216 217for.inc:218 %qaddr = getelementptr inbounds nuw i32, ptr %q, i64 %idx219 %qval = load i32, ptr %qaddr, align 4220 %add = add nsw i32 %qval, %ret.phi221 %idx.next = add nuw nsw i64 %idx, 1222 %nval = load volatile i64, ptr %n, align 8223 %cmp2 = icmp slt i64 %idx.next, %nval224 br i1 %cmp2, label %for.body, label %exit225 226exit:227 %ret = phi i32 [ %ret.phi, %for.body ], [ %add, %for.inc ]228 ret i32 %ret229}230 231; The control-flow before and after the load of qval shouldn't prevent postindex232; addressing from happening.233; FIXME: We choose postindex addressing, but the scevgep is placed in for.inc so234; during codegen we will fail to actually generate a postindex load.235define void @middle_block_load(ptr %p, ptr %q, i64 %n) {236; CHECK-LABEL: define void @middle_block_load(237; CHECK-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i64 [[N:%.*]]) {238; CHECK-NEXT: [[ENTRY:.*]]:239; CHECK-NEXT: br label %[[FOR_BODY:.*]]240; CHECK: [[FOR_BODY]]:241; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr [ [[SCEVGEP3:%.*]], %[[FOR_INC:.*]] ], [ [[P]], %[[ENTRY]] ]242; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_INC]] ], [ [[Q]], %[[ENTRY]] ]243; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[FOR_INC]] ], [ [[N]], %[[ENTRY]] ]244; CHECK-NEXT: [[PVAL:%.*]] = load i32, ptr [[LSR_IV2]], align 4245; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[PVAL]], 0246; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i8, ptr [[LSR_IV2]], i64 4247; CHECK-NEXT: br i1 [[CMP1]], label %[[IF_THEN1:.*]], label %[[IF_ELSE1:.*]]248; CHECK: [[IF_THEN1]]:249; CHECK-NEXT: tail call void @otherfn1()250; CHECK-NEXT: br label %[[IF_END:.*]]251; CHECK: [[IF_ELSE1]]:252; CHECK-NEXT: tail call void @otherfn2()253; CHECK-NEXT: br label %[[IF_END]]254; CHECK: [[IF_END]]:255; CHECK-NEXT: [[QVAL:%.*]] = load i32, ptr [[LSR_IV1]], align 4256; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[QVAL]], 0257; CHECK-NEXT: br i1 [[CMP2]], label %[[IF_THEN2:.*]], label %[[IF_ELSE2:.*]]258; CHECK: [[IF_THEN2]]:259; CHECK-NEXT: tail call void @otherfn1()260; CHECK-NEXT: br label %[[FOR_INC]]261; CHECK: [[IF_ELSE2]]:262; CHECK-NEXT: tail call void @otherfn2()263; CHECK-NEXT: br label %[[FOR_INC]]264; CHECK: [[FOR_INC]]:265; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1266; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV1]], i64 4267; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0268; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT:.*]], label %[[FOR_BODY]]269; CHECK: [[EXIT]]:270; CHECK-NEXT: ret void271;272entry:273 br label %for.body274 275for.body:276 %idx = phi i64 [ %idx.next, %for.inc ], [ 0, %entry ]277 %paddr = getelementptr inbounds nuw i32, ptr %p, i64 %idx278 %pval = load i32, ptr %paddr, align 4279 %cmp1 = icmp sgt i32 %pval, 0280 br i1 %cmp1, label %if.then1, label %if.else1281 282if.then1:283 tail call void @otherfn1()284 br label %if.end285 286if.else1:287 tail call void @otherfn2()288 br label %if.end289 290if.end:291 %qaddr = getelementptr inbounds nuw i32, ptr %q, i64 %idx292 %qval = load i32, ptr %qaddr, align 4293 %cmp2 = icmp sgt i32 %qval, 0294 br i1 %cmp2, label %if.then2, label %if.else2295 296if.then2:297 tail call void @otherfn1()298 br label %for.inc299 300if.else2:301 tail call void @otherfn2()302 br label %for.inc303 304for.inc:305 %idx.next = add nuw nsw i64 %idx, 1306 %cmp3 = icmp eq i64 %idx.next, %n307 br i1 %cmp3, label %exit, label %for.body308 309exit:310 ret void311}312 313declare dso_local void @otherfn1()314declare dso_local void @otherfn2()315