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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc %s -o - | FileCheck %s --check-prefixes=COMMON,BASE3;; Additional runlines to exercise lsr code which AArch64 normally wouldn't.4; RUN: llc %s -o - -lsr-preferred-addressing-mode=preindexed | FileCheck %s --check-prefixes=COMMON,PREINDEX5; RUN: llc %s -o - -lsr-preferred-addressing-mode=postindexed | FileCheck %s --check-prefixes=COMMON,POSTINDEX6 7target triple = "aarch64-unknown-linux-gnu"8 9define void @mulvl123_addressing(ptr %src, ptr %dst, i64 %count) #0 {10; COMMON-LABEL: mulvl123_addressing:11; COMMON: // %bb.0: // %entry12; COMMON-NEXT: ptrue p0.b13; COMMON-NEXT: mov x8, xzr14; COMMON-NEXT: .LBB0_1: // %for.body15; COMMON-NEXT: // =>This Inner Loop Header: Depth=116; COMMON-NEXT: ldr z0, [x0]17; COMMON-NEXT: ldr z1, [x0, #1, mul vl]18; COMMON-NEXT: ldr z2, [x0, #2, mul vl]19; COMMON-NEXT: ldr z3, [x0, #3, mul vl]20; COMMON-NEXT: addvl x0, x0, #521; COMMON-NEXT: umax z0.b, p0/m, z0.b, z1.b22; COMMON-NEXT: umax z2.b, p0/m, z2.b, z3.b23; COMMON-NEXT: umax z0.b, p0/m, z0.b, z2.b24; COMMON-NEXT: st1b { z0.b }, p0, [x1, x8]25; COMMON-NEXT: incb x826; COMMON-NEXT: cmp x8, x227; COMMON-NEXT: b.lo .LBB0_128; COMMON-NEXT: // %bb.2: // %for.exit29; COMMON-NEXT: ret30entry:31 %vscale = tail call i64 @llvm.vscale.i64()32 %2 = shl nuw nsw i64 %vscale, 433 %mul = shl nuw nsw i64 %vscale, 634 br label %for.body35 36for.body:37 %src.addr = phi ptr [ %src, %entry ], [ %src.addr.next, %for.body ]38 %idx = phi i64 [ 0, %entry ], [ %idx.next, %for.body ]39 %arrayidx = getelementptr inbounds i8, ptr %src.addr, i64 %idx40 %3 = load <vscale x 16 x i8>, ptr %arrayidx41 %4 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 142 %5 = load <vscale x 16 x i8>, ptr %443 %6 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 244 %7 = load <vscale x 16 x i8>, ptr %645 %8 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 346 %9 = load <vscale x 16 x i8>, ptr %847 %10 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %5)48 %11 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %7, <vscale x 16 x i8> %9)49 %12 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %10, <vscale x 16 x i8> %11)50 %src.addr.next = getelementptr inbounds i8, ptr %src.addr, i64 %mul51 %arrayidx4 = getelementptr inbounds i8, ptr %dst, i64 %idx52 store <vscale x 16 x i8> %12, ptr %arrayidx453 %idx.next = add i64 %idx, %254 %cmp = icmp ult i64 %idx.next, %count55 br i1 %cmp, label %for.body, label %for.exit56 57for.exit:58 ret void59}60 61define void @many_mulvl1_addressing(ptr %src_rows, ptr %dst_rows, i64 %stride, i64 %count) #0 {62; COMMON-LABEL: many_mulvl1_addressing:63; COMMON: // %bb.0: // %entry64; COMMON-NEXT: ptrue p0.b65; COMMON-NEXT: ptrue p1.h66; COMMON-NEXT: .LBB1_1: // %for.body67; COMMON-NEXT: // =>This Inner Loop Header: Depth=168; COMMON-NEXT: add x8, x0, x269; COMMON-NEXT: ldr z0, [x0]70; COMMON-NEXT: ld1b { z1.b }, p0/z, [x0, x2]71; COMMON-NEXT: ldr z2, [x0, #1, mul vl]72; COMMON-NEXT: ldr z3, [x8, #1, mul vl]73; COMMON-NEXT: incb x0, all, mul #274; COMMON-NEXT: subs x3, x3, #175; COMMON-NEXT: add z0.b, z0.b, z1.b76; COMMON-NEXT: add z1.b, z2.b, z3.b77; COMMON-NEXT: st1b { z0.h }, p1, [x1]78; COMMON-NEXT: st1b { z1.h }, p1, [x1, #1, mul vl]79; COMMON-NEXT: incb x1, all, mul #280; COMMON-NEXT: b.ne .LBB1_181; COMMON-NEXT: // %bb.2: // %for.exit82; COMMON-NEXT: ret83entry:84 %vscale = tail call i64 @llvm.vscale.i64()85 %mul = shl nuw nsw i64 %vscale, 586 br label %for.body87 88for.body:89 %src_row_addr = phi ptr [ %src_rows, %entry ], [ %add_ptr_src, %for.body ]90 %dst_row_addr = phi ptr [ %dst_rows, %entry ], [ %add_ptr_dst, %for.body ]91 %idx = phi i64 [ 0, %entry ], [ %inc, %for.body ]92 %2 = load <vscale x 16 x i8>, ptr %src_row_addr93 %3 = getelementptr <vscale x 16 x i8>, ptr %src_row_addr, i64 194 %4 = load <vscale x 16 x i8>, ptr %395 %arrayidx2 = getelementptr inbounds i8, ptr %src_row_addr, i64 %stride96 %5 = load <vscale x 16 x i8>, ptr %arrayidx297 %6 = getelementptr <vscale x 16 x i8>, ptr %arrayidx2, i64 198 %7 = load <vscale x 16 x i8>, ptr %699 %8 = add <vscale x 16 x i8> %2, %5100 %9 = add <vscale x 16 x i8> %4, %7101 %10 = bitcast <vscale x 16 x i8> %8 to <vscale x 8 x i16>102 %11 = trunc <vscale x 8 x i16> %10 to <vscale x 8 x i8>103 store <vscale x 8 x i8> %11, ptr %dst_row_addr104 %12 = bitcast <vscale x 16 x i8> %9 to <vscale x 8 x i16>105 %13 = getelementptr <vscale x 8 x i8>, ptr %dst_row_addr, i64 1106 %14 = trunc <vscale x 8 x i16> %12 to <vscale x 8 x i8>107 store <vscale x 8 x i8> %14, ptr %13108 %add_ptr_src = getelementptr inbounds i8, ptr %src_row_addr, i64 %mul109 %add_ptr_dst = getelementptr inbounds i8, ptr %dst_row_addr, i64 %mul110 %inc = add nuw i64 %idx, 1111 %exitcond = icmp eq i64 %inc, %count112 br i1 %exitcond, label %for.exit, label %for.body113 114for.exit:115 ret void116}117 118define void @fixed_iv_scalable_offset(ptr %src, ptr %dst, i64 %count) #0 {119; COMMON-LABEL: fixed_iv_scalable_offset:120; COMMON: // %bb.0: // %entry121; COMMON-NEXT: .LBB2_1: // %for.body122; COMMON-NEXT: // =>This Inner Loop Header: Depth=1123; COMMON-NEXT: ldr z0, [x0]124; COMMON-NEXT: ldr z1, [x0, #4, mul vl]125; COMMON-NEXT: subs x2, x2, #4126; COMMON-NEXT: add x0, x0, #16127; COMMON-NEXT: add z0.s, z0.s, z1.s128; COMMON-NEXT: str z0, [x1]129; COMMON-NEXT: add x1, x1, #16130; COMMON-NEXT: b.ne .LBB2_1131; COMMON-NEXT: // %bb.2: // %for.exit132; COMMON-NEXT: ret133entry:134 %vscale = tail call i64 @llvm.vscale.i64()135 %mul = shl nuw nsw i64 %vscale, 4136 br label %for.body137 138for.body:139 %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ]140 %src.ptr = getelementptr inbounds i32, ptr %src, i64 %iv141 %data = load <vscale x 4 x i32>, ptr %src.ptr142 %src.ptr.offset = getelementptr inbounds i32, ptr %src.ptr, i64 %mul143 %data2 = load <vscale x 4 x i32>, ptr %src.ptr.offset144 %add = add <vscale x 4 x i32> %data, %data2145 %dst.ptr = getelementptr i32, ptr %dst, i64 %iv146 store <vscale x 4 x i32> %add, ptr %dst.ptr147 %inc = add nuw i64 %iv, 4148 %exit.cond = icmp eq i64 %inc, %count149 br i1 %exit.cond, label %for.exit, label %for.body150 151for.exit:152 ret void153}154 155define void @mixed_offsets_scalable_then_fixed(ptr %src, ptr %dst, i64 %count) #0 {156; BASE-LABEL: mixed_offsets_scalable_then_fixed:157; BASE: // %bb.0: // %entry158; BASE-NEXT: incb x0, all, mul #4159; BASE-NEXT: ptrue p0.s160; BASE-NEXT: mov x8, #8 // =0x8161; BASE-NEXT: .LBB3_1: // %for.body162; BASE-NEXT: // =>This Inner Loop Header: Depth=1163; BASE-NEXT: ldr z0, [x0, #-4, mul vl]164; BASE-NEXT: ldr z1, [x0]165; BASE-NEXT: decw x2166; BASE-NEXT: ld1w { z2.s }, p0/z, [x0, x8, lsl #2]167; BASE-NEXT: incb x0168; BASE-NEXT: add z0.s, z0.s, z1.s169; BASE-NEXT: add z0.s, z0.s, z2.s170; BASE-NEXT: str z0, [x1]171; BASE-NEXT: incb x1172; BASE-NEXT: cbnz x2, .LBB3_1173; BASE-NEXT: // %bb.2: // %for.exit174; BASE-NEXT: ret175;176; PREINDEX-LABEL: mixed_offsets_scalable_then_fixed:177; PREINDEX: // %bb.0: // %entry178; PREINDEX-NEXT: incb x0, all, mul #4179; PREINDEX-NEXT: ptrue p0.s180; PREINDEX-NEXT: mov x8, #8 // =0x8181; PREINDEX-NEXT: .LBB3_1: // %for.body182; PREINDEX-NEXT: // =>This Inner Loop Header: Depth=1183; PREINDEX-NEXT: ldr z0, [x0, #-4, mul vl]184; PREINDEX-NEXT: ldr z1, [x0]185; PREINDEX-NEXT: decw x2186; PREINDEX-NEXT: ld1w { z2.s }, p0/z, [x0, x8, lsl #2]187; PREINDEX-NEXT: incb x0188; PREINDEX-NEXT: add z0.s, z0.s, z1.s189; PREINDEX-NEXT: add z0.s, z0.s, z2.s190; PREINDEX-NEXT: str z0, [x1]191; PREINDEX-NEXT: incb x1192; PREINDEX-NEXT: cbnz x2, .LBB3_1193; PREINDEX-NEXT: // %bb.2: // %for.exit194; PREINDEX-NEXT: ret195;196; POSTINDEX-LABEL: mixed_offsets_scalable_then_fixed:197; POSTINDEX: // %bb.0: // %entry198; POSTINDEX-NEXT: incb x0, all, mul #4199; POSTINDEX-NEXT: ptrue p0.s200; POSTINDEX-NEXT: mov x8, xzr201; POSTINDEX-NEXT: mov x9, #8 // =0x8202; POSTINDEX-NEXT: .LBB3_1: // %for.body203; POSTINDEX-NEXT: // =>This Inner Loop Header: Depth=1204; POSTINDEX-NEXT: ldr z0, [x0, #-4, mul vl]205; POSTINDEX-NEXT: ldr z1, [x0]206; POSTINDEX-NEXT: ld1w { z2.s }, p0/z, [x0, x9, lsl #2]207; POSTINDEX-NEXT: incb x0208; POSTINDEX-NEXT: add z0.s, z0.s, z1.s209; POSTINDEX-NEXT: add z0.s, z0.s, z2.s210; POSTINDEX-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]211; POSTINDEX-NEXT: incw x8212; POSTINDEX-NEXT: cmp x2, x8213; POSTINDEX-NEXT: b.ne .LBB3_1214; POSTINDEX-NEXT: // %bb.2: // %for.exit215; POSTINDEX-NEXT: ret216entry:217 %vscale = tail call i64 @llvm.vscale.i64()218 %mul = shl nuw nsw i64 %vscale, 4219 %vl = shl nuw nsw i64 %vscale, 2220 br label %for.body221 222for.body:223 %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ]224 %src.ptr = getelementptr inbounds i32, ptr %src, i64 %iv225 %data = load <vscale x 4 x i32>, ptr %src.ptr226 %src.ptr.sc_off = getelementptr inbounds i32, ptr %src.ptr, i64 %mul227 %data2 = load <vscale x 4 x i32>, ptr %src.ptr.sc_off228 %src.ptr.fx_off = getelementptr inbounds i32, ptr %src.ptr.sc_off, i64 8229 %data3 = load <vscale x 4 x i32>, ptr %src.ptr.fx_off230 %add = add <vscale x 4 x i32> %data, %data2231 %add2 = add <vscale x 4 x i32> %add, %data3232 %dst.ptr = getelementptr i32, ptr %dst, i64 %iv233 store <vscale x 4 x i32> %add2, ptr %dst.ptr234 %inc = add nuw i64 %iv, %vl235 %exit.cond = icmp eq i64 %inc, %count236 br i1 %exit.cond, label %for.exit, label %for.body237 238for.exit:239 ret void240}241 242define void @mixed_offsets_fixed_then_scalable(ptr %src, ptr %dst, i64 %count) #0 {243; COMMON-LABEL: mixed_offsets_fixed_then_scalable:244; COMMON: // %bb.0: // %entry245; COMMON-NEXT: mov x9, x0246; COMMON-NEXT: ptrue p0.s247; COMMON-NEXT: mov x8, xzr248; COMMON-NEXT: incb x9, all, mul #4249; COMMON-NEXT: mov x10, #8 // =0x8250; COMMON-NEXT: add x9, x9, #32251; COMMON-NEXT: .LBB4_1: // %for.body252; COMMON-NEXT: // =>This Inner Loop Header: Depth=1253; COMMON-NEXT: add x11, x0, x8, lsl #2254; COMMON-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]255; COMMON-NEXT: ld1w { z2.s }, p0/z, [x9, x8, lsl #2]256; COMMON-NEXT: ld1w { z1.s }, p0/z, [x11, x10, lsl #2]257; COMMON-NEXT: add z0.s, z0.s, z1.s258; COMMON-NEXT: add z0.s, z0.s, z2.s259; COMMON-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]260; COMMON-NEXT: incw x8261; COMMON-NEXT: cmp x2, x8262; COMMON-NEXT: b.ne .LBB4_1263; COMMON-NEXT: // %bb.2: // %for.exit264; COMMON-NEXT: ret265entry:266 %vscale = tail call i64 @llvm.vscale.i64()267 %mul = shl nuw nsw i64 %vscale, 4268 %vl = shl nuw nsw i64 %vscale, 2269 br label %for.body270 271for.body:272 %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ]273 %src.ptr = getelementptr inbounds i32, ptr %src, i64 %iv274 %data = load <vscale x 4 x i32>, ptr %src.ptr275 %src.ptr.fx_off = getelementptr inbounds i32, ptr %src.ptr, i64 8276 %data2 = load <vscale x 4 x i32>, ptr %src.ptr.fx_off277 %src.ptr.sc_off = getelementptr inbounds i32, ptr %src.ptr.fx_off, i64 %mul278 %data3 = load <vscale x 4 x i32>, ptr %src.ptr.sc_off279 %add = add <vscale x 4 x i32> %data, %data2280 %add2 = add <vscale x 4 x i32> %add, %data3281 %dst.ptr = getelementptr i32, ptr %dst, i64 %iv282 store <vscale x 4 x i32> %add2, ptr %dst.ptr283 %inc = add nuw i64 %iv, %vl284 %exit.cond = icmp eq i64 %inc, %count285 br i1 %exit.cond, label %for.exit, label %for.body286 287for.exit:288 ret void289}290 291;; FIXME: There's an opportunity here (that we currently miss) to define the phi292;; on the middle access, and have negative and positive scalable immediates.293;;294;; Currently we generate a scalable offset for the load in range of the base,295;; and a register to store the offset for the access that's out of range of the296;; base (but in range of the other).297;;298define void @three_access_wide_gap(ptr %src, ptr %dst, i64 %count) #0 {299; BASE-LABEL: three_access_wide_gap:300; BASE: // %bb.0: // %entry301; BASE-NEXT: .LBB5_1: // %for.body302; BASE-NEXT: // =>This Inner Loop Header: Depth=1303; BASE-NEXT: ldr z0, [x0]304; BASE-NEXT: ldr z1, [x0, #4, mul vl]305; BASE-NEXT: decw x2306; BASE-NEXT: ldr z2, [x0, #8, mul vl]307; BASE-NEXT: incb x0308; BASE-NEXT: add z0.s, z0.s, z1.s309; BASE-NEXT: add z0.s, z0.s, z2.s310; BASE-NEXT: str z0, [x1]311; BASE-NEXT: incb x1312; BASE-NEXT: cbnz x2, .LBB5_1313; BASE-NEXT: // %bb.2: // %for.exit314; BASE-NEXT: ret315;316; PREINDEX-LABEL: three_access_wide_gap:317; PREINDEX: // %bb.0: // %entry318; PREINDEX-NEXT: .LBB5_1: // %for.body319; PREINDEX-NEXT: // =>This Inner Loop Header: Depth=1320; PREINDEX-NEXT: ldr z0, [x0]321; PREINDEX-NEXT: ldr z1, [x0, #4, mul vl]322; PREINDEX-NEXT: decw x2323; PREINDEX-NEXT: ldr z2, [x0, #8, mul vl]324; PREINDEX-NEXT: incb x0325; PREINDEX-NEXT: add z0.s, z0.s, z1.s326; PREINDEX-NEXT: add z0.s, z0.s, z2.s327; PREINDEX-NEXT: str z0, [x1]328; PREINDEX-NEXT: incb x1329; PREINDEX-NEXT: cbnz x2, .LBB5_1330; PREINDEX-NEXT: // %bb.2: // %for.exit331; PREINDEX-NEXT: ret332;333; POSTINDEX-LABEL: three_access_wide_gap:334; POSTINDEX: // %bb.0: // %entry335; POSTINDEX-NEXT: ptrue p0.s336; POSTINDEX-NEXT: mov x8, xzr337; POSTINDEX-NEXT: .LBB5_1: // %for.body338; POSTINDEX-NEXT: // =>This Inner Loop Header: Depth=1339; POSTINDEX-NEXT: ldr z0, [x0]340; POSTINDEX-NEXT: ldr z1, [x0, #4, mul vl]341; POSTINDEX-NEXT: ldr z2, [x0, #8, mul vl]342; POSTINDEX-NEXT: incb x0343; POSTINDEX-NEXT: add z0.s, z0.s, z1.s344; POSTINDEX-NEXT: add z0.s, z0.s, z2.s345; POSTINDEX-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]346; POSTINDEX-NEXT: incw x8347; POSTINDEX-NEXT: cmp x2, x8348; POSTINDEX-NEXT: b.ne .LBB5_1349; POSTINDEX-NEXT: // %bb.2: // %for.exit350; POSTINDEX-NEXT: ret351entry:352 %vscale = tail call i64 @llvm.vscale.i64()353 %mul = mul nuw nsw i64 %vscale, 16354 %mul2 = mul nuw nsw i64 %vscale, 16355 %vl = mul nuw nsw i64 %vscale, 4356 br label %for.body357 358for.body:359 %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ]360 %src.ptr = getelementptr inbounds i32, ptr %src, i64 %iv361 %data = load <vscale x 4 x i32>, ptr %src.ptr362 %src.ptr.sc_off = getelementptr inbounds i32, ptr %src.ptr, i64 %mul363 %data2 = load <vscale x 4 x i32>, ptr %src.ptr.sc_off364 %src.ptr.sc_off2 = getelementptr inbounds i32, ptr %src.ptr.sc_off, i64 %mul2365 %data3 = load <vscale x 4 x i32>, ptr %src.ptr.sc_off2366 %add = add <vscale x 4 x i32> %data, %data2367 %add2 = add <vscale x 4 x i32> %add, %data3368 %dst.ptr = getelementptr i32, ptr %dst, i64 %iv369 store <vscale x 4 x i32> %add2, ptr %dst.ptr370 %inc = add nuw i64 %iv, %vl371 %exit.cond = icmp eq i64 %inc, %count372 br i1 %exit.cond, label %for.exit, label %for.body373 374for.exit:375 ret void376}377 378;; Here are two writes that should be `16 * vscale * vscale` apart, so MUL VL379;; addressing cannot be used to offset the second write, as for example,380;; `#4, mul vl` would only be an offset of `16 * vscale` (dropping a vscale).381define void @vscale_squared_offset(ptr %alloc) #0 {382; COMMON-LABEL: vscale_squared_offset:383; COMMON: // %bb.0: // %entry384; COMMON-NEXT: rdvl x9, #1385; COMMON-NEXT: rdvl x10, #4386; COMMON-NEXT: fmov z0.s, #4.00000000387; COMMON-NEXT: lsr x9, x9, #4388; COMMON-NEXT: fmov z1.s, #8.00000000389; COMMON-NEXT: mov x8, xzr390; COMMON-NEXT: ptrue p0.s, vl1391; COMMON-NEXT: umull x9, w9, w10392; COMMON-NEXT: cntw x10393; COMMON-NEXT: cmp x8, x10394; COMMON-NEXT: b.ge .LBB6_2395; COMMON-NEXT: .LBB6_1: // %for.body396; COMMON-NEXT: // =>This Inner Loop Header: Depth=1397; COMMON-NEXT: add x11, x0, x9398; COMMON-NEXT: st1w { z0.s }, p0, [x0]399; COMMON-NEXT: incb x0400; COMMON-NEXT: st1w { z1.s }, p0, [x11]401; COMMON-NEXT: add x8, x8, #1402; COMMON-NEXT: cmp x8, x10403; COMMON-NEXT: b.lt .LBB6_1404; COMMON-NEXT: .LBB6_2: // %for.exit405; COMMON-NEXT: ret406entry:407 %vscale = call i64 @llvm.vscale.i64()408 %c4_vscale = mul i64 %vscale, 4409 br label %for.check410for.check:411 %i = phi i64 [ %next_i, %for.body ], [ 0, %entry ]412 %is_lt = icmp slt i64 %i, %c4_vscale413 br i1 %is_lt, label %for.body, label %for.exit414for.body:415 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 0, i64 1)416 %upper_offset = mul i64 %i, %c4_vscale417 %upper_ptr = getelementptr float, ptr %alloc, i64 %upper_offset418 call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 4.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer), ptr %upper_ptr, i32 4, <vscale x 4 x i1> %mask)419 %lower_i = add i64 %i, %c4_vscale420 %lower_offset = mul i64 %lower_i, %c4_vscale421 %lower_ptr = getelementptr float, ptr %alloc, i64 %lower_offset422 call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 8.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer), ptr %lower_ptr, i32 4, <vscale x 4 x i1> %mask)423 %next_i = add i64 %i, 1424 br label %for.check425for.exit:426 ret void427}428 429attributes #0 = { "target-features"="+sve2" vscale_range(1,16) }430