161 lines · plain
1; RUN: opt -S -mtriple=amdgcn-- -mcpu=bonaire -loop-reduce < %s | FileCheck -check-prefix=OPT %s2 3; Test that loops with different maximum offsets for different address4; spaces are correctly handled.5 6; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_i32(7; OPT: .lr.ph.preheader:8; OPT: %scevgep2 = getelementptr i8, ptr addrspace(1) %arg1, i64 40959; OPT: br label %.lr.ph10; OPT: {{^}}.lr.ph:11; OPT: %lsr.iv3 = phi ptr addrspace(1) [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]12; OPT: load i8, ptr addrspace(1) %lsr.iv3, align 113; OPT: %scevgep4 = getelementptr i8, ptr addrspace(1) %lsr.iv3, i64 114define amdgpu_kernel void @test_global_addressing_loop_uniform_index_max_offset_i32(ptr addrspace(1) noalias nocapture %arg0, ptr addrspace(1) noalias nocapture readonly %arg1, i32 %n) #0 {15bb:16 %tmp = icmp sgt i32 %n, 017 br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge18 19.lr.ph.preheader: ; preds = %bb20 br label %.lr.ph21 22._crit_edge.loopexit: ; preds = %.lr.ph23 br label %._crit_edge24 25._crit_edge: ; preds = %._crit_edge.loopexit, %bb26 ret void27 28.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader29 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]30 %tmp1 = add nuw nsw i64 %indvars.iv, 409531 %tmp2 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %tmp132 %tmp3 = load i8, ptr addrspace(1) %tmp2, align 133 %tmp4 = sext i8 %tmp3 to i3234 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg0, i64 %indvars.iv35 %tmp6 = load i32, ptr addrspace(1) %tmp5, align 436 %tmp7 = add nsw i32 %tmp6, %tmp437 store i32 %tmp7, ptr addrspace(1) %tmp5, align 438 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 139 %lftr.wideiv = trunc i64 %indvars.iv.next to i3240 %exitcond = icmp eq i32 %lftr.wideiv, %n41 br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph42}43 44; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_p1_i32(45; OPT: {{^}}.lr.ph.preheader:46; OPT: %scevgep2 = getelementptr i8, ptr addrspace(1) %arg1, i64 409647; OPT: br label %.lr.ph48 49; OPT: {{^}}.lr.ph:50; OPT: %lsr.iv3 = phi ptr addrspace(1) [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]51; OPT: %scevgep4 = getelementptr i8, ptr addrspace(1) %lsr.iv3, i64 152define amdgpu_kernel void @test_global_addressing_loop_uniform_index_max_offset_p1_i32(ptr addrspace(1) noalias nocapture %arg0, ptr addrspace(1) noalias nocapture readonly %arg1, i32 %n) #0 {53bb:54 %tmp = icmp sgt i32 %n, 055 br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge56 57.lr.ph.preheader: ; preds = %bb58 br label %.lr.ph59 60._crit_edge.loopexit: ; preds = %.lr.ph61 br label %._crit_edge62 63._crit_edge: ; preds = %._crit_edge.loopexit, %bb64 ret void65 66.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader67 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]68 %tmp1 = add nuw nsw i64 %indvars.iv, 409669 %tmp2 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %tmp170 %tmp3 = load i8, ptr addrspace(1) %tmp2, align 171 %tmp4 = sext i8 %tmp3 to i3272 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg0, i64 %indvars.iv73 %tmp6 = load i32, ptr addrspace(1) %tmp5, align 474 %tmp7 = add nsw i32 %tmp6, %tmp475 store i32 %tmp7, ptr addrspace(1) %tmp5, align 476 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 177 %lftr.wideiv = trunc i64 %indvars.iv.next to i3278 %exitcond = icmp eq i32 %lftr.wideiv, %n79 br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph80}81 82; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_i32(83; OPT: .lr.ph.preheader:84; OPT: %scevgep2 = getelementptr i8, ptr addrspace(3) %arg1, i32 6553585; OPT: br label %.lr.ph86; OPT: {{^}}.lr.ph87; OPT: %lsr.iv3 = phi ptr addrspace(3) [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]88; OPT: %tmp4 = load i8, ptr addrspace(3) %lsr.iv3, align 189; OPT: %scevgep4 = getelementptr i8, ptr addrspace(3) %lsr.iv3, i32 190define amdgpu_kernel void @test_local_addressing_loop_uniform_index_max_offset_i32(ptr addrspace(1) noalias nocapture %arg0, ptr addrspace(3) noalias nocapture readonly %arg1, i32 %n) #0 {91bb:92 %tmp = icmp sgt i32 %n, 093 br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge94 95.lr.ph.preheader: ; preds = %bb96 br label %.lr.ph97 98._crit_edge.loopexit: ; preds = %.lr.ph99 br label %._crit_edge100 101._crit_edge: ; preds = %._crit_edge.loopexit, %bb102 ret void103 104.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader105 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]106 %tmp1 = add nuw nsw i64 %indvars.iv, 65535107 %tmp2 = trunc i64 %tmp1 to i32108 %tmp3 = getelementptr inbounds i8, ptr addrspace(3) %arg1, i32 %tmp2109 %tmp4 = load i8, ptr addrspace(3) %tmp3, align 1110 %tmp5 = sext i8 %tmp4 to i32111 %tmp6 = getelementptr inbounds i32, ptr addrspace(1) %arg0, i64 %indvars.iv112 %tmp7 = load i32, ptr addrspace(1) %tmp6, align 4113 %tmp8 = add nsw i32 %tmp7, %tmp5114 store i32 %tmp8, ptr addrspace(1) %tmp6, align 4115 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1116 %lftr.wideiv = trunc i64 %indvars.iv.next to i32117 %exitcond = icmp eq i32 %lftr.wideiv, %n118 br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph119}120 121; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_p1_i32(122; OPT: {{^}}.lr.ph.preheader:123; OPT: %scevgep2 = getelementptr i8, ptr addrspace(3) %arg1, i32 65536124; OPT: br label %.lr.ph125 126; OPT: {{^}}.lr.ph:127; OPT: %lsr.iv3 = phi ptr addrspace(3) [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]128; OPT: %scevgep4 = getelementptr i8, ptr addrspace(3) %lsr.iv3, i32 1129define amdgpu_kernel void @test_local_addressing_loop_uniform_index_max_offset_p1_i32(ptr addrspace(1) noalias nocapture %arg0, ptr addrspace(3) noalias nocapture readonly %arg1, i32 %n) #0 {130bb:131 %tmp = icmp sgt i32 %n, 0132 br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge133 134.lr.ph.preheader: ; preds = %bb135 br label %.lr.ph136 137._crit_edge.loopexit: ; preds = %.lr.ph138 br label %._crit_edge139 140._crit_edge: ; preds = %._crit_edge.loopexit, %bb141 ret void142 143.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader144 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]145 %tmp1 = add nuw nsw i64 %indvars.iv, 65536146 %tmp2 = trunc i64 %tmp1 to i32147 %tmp3 = getelementptr inbounds i8, ptr addrspace(3) %arg1, i32 %tmp2148 %tmp4 = load i8, ptr addrspace(3) %tmp3, align 1149 %tmp5 = sext i8 %tmp4 to i32150 %tmp6 = getelementptr inbounds i32, ptr addrspace(1) %arg0, i64 %indvars.iv151 %tmp7 = load i32, ptr addrspace(1) %tmp6, align 4152 %tmp8 = add nsw i32 %tmp7, %tmp5153 store i32 %tmp8, ptr addrspace(1) %tmp6, align 4154 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1155 %lftr.wideiv = trunc i64 %indvars.iv.next to i32156 %exitcond = icmp eq i32 %lftr.wideiv, %n157 br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph158}159 160attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hawaii" "use-soft-float"="false" }161