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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=amdgcn -loop-reduce -S < %s | FileCheck %s3; REQUIRES: asserts4 5; Test that LSR does not attempt to extend a pointer type to an integer type,6; which causes a SCEV analysis assertion.7 8@gVar = external hidden local_unnamed_addr addrspace(3) global [1024 x double], align 169 10define amdgpu_kernel void @scaledregtest() local_unnamed_addr {11; CHECK-LABEL: @scaledregtest(12; CHECK-NEXT: entry:13; CHECK-NEXT: br label [[FOR_BODY:%.*]]14; CHECK: loopexit:15; CHECK-NEXT: [[SCEVGEP11_LCSSA:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP11:%.*]], [[FOR_BODY]] ]16; CHECK-NEXT: [[SCEVGEP13_LCSSA:%.*]] = phi ptr [ [[SCEVGEP13:%.*]], [[FOR_BODY]] ]17; CHECK-NEXT: br label [[FOR_BODY_1:%.*]]18; CHECK: for.body.1:19; CHECK-NEXT: [[LSR_IV5:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP6:%.*]], [[FOR_BODY_1]] ], [ [[SCEVGEP11_LCSSA]], [[LOOPEXIT:%.*]] ]20; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[FOR_BODY_1]] ], [ [[SCEVGEP13_LCSSA]], [[LOOPEXIT]] ]21; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspace(5) [[LSR_IV5]], align 822; CHECK-NEXT: store ptr [[TMP0]], ptr [[LSR_IV1]], align 823; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 824; CHECK-NEXT: [[SCEVGEP6]] = getelementptr i8, ptr addrspace(5) [[LSR_IV5]], i32 825; CHECK-NEXT: br label [[FOR_BODY_1]]26; CHECK: for.body:27; CHECK-NEXT: [[LSR_IV12:%.*]] = phi ptr [ [[SCEVGEP13]], [[FOR_BODY]] ], [ null, [[ENTRY:%.*]] ]28; CHECK-NEXT: [[LSR_IV10:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP11]], [[FOR_BODY]] ], [ null, [[ENTRY]] ]29; CHECK-NEXT: [[SCEVGEP11]] = getelementptr i8, ptr addrspace(5) [[LSR_IV10]], i32 6430; CHECK-NEXT: [[SCEVGEP13]] = getelementptr i8, ptr [[LSR_IV12]], i64 6431; CHECK-NEXT: br i1 false, label [[LOOPEXIT]], label [[FOR_BODY]]32;33entry:34 br label %for.body35 36loopexit:37 %conv = zext i32 %inc to i6438 br label %for.body.139 40for.body.1:41 %conv.1 = phi i64 [ %conv.2, %for.body.1 ], [ %conv, %loopexit ]42 %I.1 = phi i32 [ %inc.1, %for.body.1 ], [ %inc, %loopexit ]43 %idxprom = trunc i64 %conv.1 to i3244 %arrayidx = getelementptr inbounds ptr, ptr addrspace(5) null, i32 %idxprom45 %0 = load ptr, ptr addrspace(5) %arrayidx, align 846 %arrayidx.1 = getelementptr inbounds ptr, ptr null, i64 %conv.147 store ptr %0, ptr %arrayidx.1, align 848 %inc.1 = add nuw nsw i32 %I.1, 149 %conv.2 = zext i32 %inc.1 to i6450 br label %for.body.151 52for.body:53 %I = phi i32 [ 0, %entry ], [ %inc, %for.body ]54 %inc = add nuw nsw i32 %I, 855 br i1 false, label %loopexit, label %for.body56}57 58define protected amdgpu_kernel void @baseregtest(i32 %n, i32 %lda, i1 %arg) local_unnamed_addr {59; CHECK-LABEL: @baseregtest(60; CHECK-NEXT: entry:61; CHECK-NEXT: br i1 %arg, label [[EXIT:%.*]], label [[IF_END:%.*]]62; CHECK: if.end:63; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @foo()64; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 365; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) @gVar, i32 [[TMP1]]66; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[N:%.*]], 367; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP0]] to i6468; CHECK-NEXT: [[TMP4:%.*]] = shl nsw i64 [[TMP3]], 369; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr addrspace(1) null, i64 [[TMP4]]70; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[LDA:%.*]] to i6471; CHECK-NEXT: [[TMP6:%.*]] = shl nsw i64 [[TMP5]], 372; CHECK-NEXT: br label [[FOR_BODY:%.*]]73; CHECK: for.body:74; CHECK-NEXT: [[LSR_IV3:%.*]] = phi ptr addrspace(1) [ [[SCEVGEP4:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP2]], [[IF_END]] ]75; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr addrspace(3) [ [[SCEVGEP1:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP]], [[IF_END]] ]76; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr addrspace(1) [[LSR_IV3]], align 877; CHECK-NEXT: store double [[TMP7]], ptr addrspace(3) [[LSR_IV]], align 878; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, ptr addrspace(3) [[LSR_IV]], i32 [[TMP2]]79; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i8, ptr addrspace(1) [[LSR_IV3]], i64 [[TMP6]]80; CHECK-NEXT: br label [[FOR_BODY]]81; CHECK: exit:82; CHECK-NEXT: ret void83;84entry:85 br i1 %arg, label %exit, label %if.end86 87if.end:88 %0 = tail call i32 @foo()89 br label %for.body90 91for.body:92 %i = phi i32 [ %inc, %for.body ], [ 0, %if.end ]93 %mul1 = mul nsw i32 %i, %lda94 %add1 = add nsw i32 %mul1, %095 %idxprom = sext i32 %add1 to i6496 %arrayidx = getelementptr inbounds double, ptr addrspace(1) null, i64 %idxprom97 %1 = load double, ptr addrspace(1) %arrayidx, align 898 %mul2 = mul nsw i32 %i, %n99 %add2 = add nsw i32 %mul2, %0100 %arrayidx9110 = getelementptr inbounds [1024 x double], ptr addrspace(3) @gVar, i32 0, i32 %add2101 store double %1, ptr addrspace(3) %arrayidx9110, align 8102 %inc = add nuw nsw i32 %i, 1103 br label %for.body104 105exit:106 ret void107}108 109declare i32 @foo()110