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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=amdgcn -mcpu=bonaire -loop-reduce -S < %s | FileCheck %s3 4; Test various conditions where OptimizeLoopTermCond doesn't look at a5; memory instruction use and fails to find the address space.6 7define amdgpu_kernel void @local_cmp_user(i32 %arg0) nounwind {8; CHECK-LABEL: @local_cmp_user(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 111; CHECK-NEXT: br label [[BB11:%.*]]12; CHECK: bb11:13; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ]14; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]15; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -116; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 217; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 018; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]]19; CHECK: bb:20; CHECK-NEXT: [[T:%.*]] = load ptr addrspace(3), ptr addrspace(3) undef, align 421; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[T]], i32 [[LSR_IV_NEXT2]]22; CHECK-NEXT: [[C1:%.*]] = icmp ne ptr addrspace(3) [[SCEVGEP]], null23; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]]24; CHECK: bb13:25; CHECK-NEXT: unreachable26;27entry:28 br label %bb1129 30bb11: ; preds = %bb, %entry31 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]32 %ii = shl i32 %i, 133 %c0 = icmp eq i32 %i, %arg034 br i1 %c0, label %bb13, label %bb35 36bb: ; preds = %bb1137 %t = load ptr addrspace(3), ptr addrspace(3) undef, align 438 %p = getelementptr i8, ptr addrspace(3) %t, i32 %ii39 %c1 = icmp ne ptr addrspace(3) %p, null40 %i.next = add i32 %i, 141 br i1 %c1, label %bb11, label %bb1342 43bb13: ; preds = %bb, %bb1144 unreachable45}46 47define amdgpu_kernel void @global_cmp_user(i64 %arg0) nounwind {48; CHECK-LABEL: @global_cmp_user(49; CHECK-NEXT: entry:50; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[ARG0:%.*]], 151; CHECK-NEXT: br label [[BB11:%.*]]52; CHECK: bb11:53; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ]54; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]55; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -156; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i64 [[LSR_IV1]], 257; CHECK-NEXT: [[C0:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 058; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]]59; CHECK: bb:60; CHECK-NEXT: [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 861; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[LSR_IV_NEXT2]]62; CHECK-NEXT: [[C1:%.*]] = icmp ne ptr addrspace(1) [[SCEVGEP]], null63; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]]64; CHECK: bb13:65; CHECK-NEXT: unreachable66;67entry:68 br label %bb1169 70bb11: ; preds = %bb, %entry71 %i = phi i64 [ 0, %entry ], [ %i.next, %bb ]72 %ii = shl i64 %i, 173 %c0 = icmp eq i64 %i, %arg074 br i1 %c0, label %bb13, label %bb75 76bb: ; preds = %bb1177 %t = load ptr addrspace(1), ptr addrspace(1) undef, align 878 %p = getelementptr i8, ptr addrspace(1) %t, i64 %ii79 %c1 = icmp ne ptr addrspace(1) %p, null80 %i.next = add i64 %i, 181 br i1 %c1, label %bb11, label %bb1382 83bb13: ; preds = %bb, %bb1184 unreachable85}86 87define amdgpu_kernel void @global_gep_user(i32 %arg0) nounwind {88; CHECK-LABEL: @global_gep_user(89; CHECK-NEXT: entry:90; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 191; CHECK-NEXT: br label [[BB11:%.*]]92; CHECK: bb11:93; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ]94; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]95; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -196; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 297; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 098; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]]99; CHECK: bb:100; CHECK-NEXT: [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 8101; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[LSR_IV1]] to i64102; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[IDXPROM]]103; CHECK-NEXT: [[C1:%.*]] = icmp ne ptr addrspace(1) [[P]], null104; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]]105; CHECK: bb13:106; CHECK-NEXT: unreachable107;108entry:109 br label %bb11110 111bb11: ; preds = %bb, %entry112 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]113 %ii = shl i32 %i, 1114 %c0 = icmp eq i32 %i, %arg0115 br i1 %c0, label %bb13, label %bb116 117bb: ; preds = %bb11118 %t = load ptr addrspace(1), ptr addrspace(1) undef, align 8119 %idxprom = sext i32 %ii to i64120 %p = getelementptr i8, ptr addrspace(1) %t, i64 %idxprom121 %c1 = icmp ne ptr addrspace(1) %p, null122 %i.next = add i32 %i, 1123 br i1 %c1, label %bb11, label %bb13124 125bb13: ; preds = %bb, %bb11126 unreachable127}128 129define amdgpu_kernel void @global_sext_scale_user(i32 %arg0) nounwind {130; CHECK-LABEL: @global_sext_scale_user(131; CHECK-NEXT: entry:132; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1133; CHECK-NEXT: br label [[BB11:%.*]]134; CHECK: bb11:135; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ]136; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]137; CHECK-NEXT: [[II_EXT:%.*]] = sext i32 [[LSR_IV1]] to i64138; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1139; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2140; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0141; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]]142; CHECK: bb:143; CHECK-NEXT: [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 8144; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[II_EXT]]145; CHECK-NEXT: [[C1:%.*]] = icmp ne ptr addrspace(1) [[P]], null146; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]]147; CHECK: bb13:148; CHECK-NEXT: unreachable149;150entry:151 br label %bb11152 153bb11: ; preds = %bb, %entry154 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]155 %ii = shl i32 %i, 1156 %ii.ext = sext i32 %ii to i64157 %c0 = icmp eq i32 %i, %arg0158 br i1 %c0, label %bb13, label %bb159 160bb: ; preds = %bb11161 %t = load ptr addrspace(1), ptr addrspace(1) undef, align 8162 %p = getelementptr i8, ptr addrspace(1) %t, i64 %ii.ext163 %c1 = icmp ne ptr addrspace(1) %p, null164 %i.next = add i32 %i, 1165 br i1 %c1, label %bb11, label %bb13166 167bb13: ; preds = %bb, %bb11168 unreachable169}170