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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2 3@array = external addrspace(4) constant [32 x [800 x i32]], align 44 5; GCN-LABEL: {{^}}test_lsr_voidty:6define amdgpu_kernel void @test_lsr_voidty(i1 %arg) {7entry:8 br label %for.body9 10for.body: ; preds = %for.body.i, %entry11 br label %for.body.i12 13for.body.i: ; preds = %for.body.i, %for.body14 %ij = phi i32 [ 0, %for.body ], [ %inc14, %for.body.i ]15 %tmp = load i32, ptr addrspace(5) undef, align 416 %inc13 = or i32 %ij, 217 %shl = shl i32 1, 018 %and = and i32 %shl, %tmp19 %tobool = icmp eq i32 %and, 020 %add = mul nuw nsw i32 %inc13, 521 %tmp1 = zext i32 %add to i6422 %arrayidx8 = getelementptr inbounds [32 x [800 x i32]], ptr addrspace(4) @array, i64 0, i64 undef, i64 %tmp123 %tmp2 = load i32, ptr addrspace(4) %arrayidx8, align 424 %and9 = select i1 %tobool, i32 0, i32 %tmp225 %xor = xor i32 undef, %and926 %inc1 = or i32 %ij, 327 %add2 = mul nuw nsw i32 %inc1, 528 %add6 = add nuw nsw i32 %add2, 129 %tmp3 = zext i32 %add6 to i6430 %arrayidx9 = getelementptr inbounds [32 x [800 x i32]], ptr addrspace(4) @array, i64 0, i64 undef, i64 %tmp331 %tmp5 = load <4 x i32>, ptr addrspace(4) %arrayidx9, align 432 %reorder_shuffle2 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>33 %tmp6 = select <4 x i1> undef, <4 x i32> zeroinitializer, <4 x i32> %reorder_shuffle234 %inc14 = add nuw nsw i32 %ij, 435 br i1 %arg, label %for.body, label %for.body.i36}37