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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s3 4; Test for assert resulting from inconsistent isLegalAddressingMode5; answers when the address space was dropped from the query.6 7%0 = type { i32, double, i32, float }8 9 10define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type() #0 {11; CHECK-LABEL: define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type(12; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: [[BB:.*]]:14; CHECK-NEXT: br label %[[BB1:.*]]15; CHECK: [[BB1]]:16; CHECK-NEXT: [[TMP:%.*]] = phi ptr addrspace(3) [ undef, %[[BB]] ], [ [[TMP18:%.*]], %[[BB17:.*]] ]17; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 818; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr addrspace(3) [[SCEVGEP1]], align 819; CHECK-NEXT: br label %[[BB4:.*]]20; CHECK: [[BB4]]:21; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB5:.*]]22; CHECK: [[BB5]]:23; CHECK-NEXT: unreachable24; CHECK: [[BB8]]:25; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) [[TMP]], align 426; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 0, [[TMP10]]27; CHECK-NEXT: br i1 [[TMP11]], label %[[BB12:.*]], label %[[BB17]]28; CHECK: [[BB12]]:29; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 1630; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) [[SCEVGEP]], align 431; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 0, [[TMP14]]32; CHECK-NEXT: br i1 [[TMP15]], label %[[BB16:.*]], label %[[BB17]]33; CHECK: [[BB16]]:34; CHECK-NEXT: unreachable35; CHECK: [[BB17]]:36; CHECK-NEXT: [[TMP18]] = getelementptr inbounds [[TMP0:%.*]], ptr addrspace(3) [[TMP]], i64 237; CHECK-NEXT: br label %[[BB1]]38;39bb:40 br label %bb141 42bb1: ; preds = %bb17, %bb43 %tmp = phi ptr addrspace(3) [ undef, %bb ], [ %tmp18, %bb17 ]44 %tmp2 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 0, i32 145 %tmp3 = load double, ptr addrspace(3) %tmp2, align 846 br label %bb447 48bb4: ; preds = %bb149 br i1 false, label %bb8, label %bb550 51bb5: ; preds = %bb452 unreachable53 54bb8: ; preds = %bb455 %tmp10 = load i32, ptr addrspace(3) %tmp, align 456 %tmp11 = icmp eq i32 0, %tmp1057 br i1 %tmp11, label %bb12, label %bb1758 59bb12: ; preds = %bb860 %tmp13 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 0, i32 261 %tmp14 = load i32, ptr addrspace(3) %tmp13, align 462 %tmp15 = icmp eq i32 0, %tmp1463 br i1 %tmp15, label %bb16, label %bb1764 65bb16: ; preds = %bb1266 unreachable67 68bb17: ; preds = %bb12, %bb869 %tmp18 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 270 br label %bb171}72 73define void @lsr_crash_preserve_addrspace_unknown_type2(ptr addrspace(5) %array, ptr addrspace(3) %array2) {74; CHECK-LABEL: define void @lsr_crash_preserve_addrspace_unknown_type2(75; CHECK-SAME: ptr addrspace(5) [[ARRAY:%.*]], ptr addrspace(3) [[ARRAY2:%.*]]) {76; CHECK-NEXT: [[ENTRY:.*]]:77; CHECK-NEXT: br label %[[FOR_BODY:.*]]78; CHECK: [[FOR_BODY]]:79; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_INC:.*]] ], [ 0, %[[ENTRY]] ]80; CHECK-NEXT: [[IDX:%.*]] = getelementptr i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]81; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i8, ptr addrspace(3) [[ARRAY2]], i32 [[J]]82; CHECK-NEXT: [[T:%.*]] = getelementptr i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]83; CHECK-NEXT: [[N8:%.*]] = load i8, ptr addrspace(5) [[T]], align 484; CHECK-NEXT: [[N7:%.*]] = getelementptr i8, ptr addrspace(5) [[T]], i32 4285; CHECK-NEXT: [[N9:%.*]] = load i8, ptr addrspace(5) [[N7]], align 486; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[J]], 4287; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN17:.*]], label %[[FOR_INC]]88; CHECK: [[IF_THEN17]]:89; CHECK-NEXT: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)90; CHECK-NEXT: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)91; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[IDX]], i8 42, i64 42, i1 false)92; CHECK-NEXT: br label %[[FOR_INC]]93; CHECK: [[FOR_INC]]:94; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i1 [[CMP]], true95; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[J]], 196; CHECK-NEXT: br i1 [[EXITCOND]], label %[[END:.*]], label %[[FOR_BODY]]97; CHECK: [[END]]:98; CHECK-NEXT: ret void99;100entry:101 br label %for.body102 103for.body: ; preds = %entry, %for.inc104 %j = phi i32 [ %add, %for.inc ], [ 0, %entry ]105 %idx = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j106 %idx1 = getelementptr inbounds i8, ptr addrspace(3) %array2, i32 %j107 %t = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j108 %n8 = load i8, ptr addrspace(5) %t, align 4109 %n7 = getelementptr inbounds i8, ptr addrspace(5) %t, i32 42110 %n9 = load i8, ptr addrspace(5) %n7, align 4111 %cmp = icmp sgt i32 %j, 42112 %add = add nuw nsw i32 %j, 1113 br i1 %cmp, label %if.then17, label %for.inc114 115if.then17: ; preds = %for.body116 call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)117 call void @llvm.memmove.p5.p5.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)118 call void @llvm.memset.p5.i64(ptr addrspace(5) %idx, i8 42, i64 42, i1 false)119 br label %for.inc120 121for.inc: ; preds = %for.body, %if.then17122 %exitcond = icmp eq i1 %cmp, 1123 br i1 %exitcond, label %end, label %for.body124 125end: ; preds = %for.inc126 ret void127}128 129declare void @llvm.memcpy.p5.p5.i64(ptr addrspace(5), ptr addrspace(3), i64, i1)130declare void @llvm.memmove.p5.p5.i64(ptr addrspace(5), ptr addrspace(3), i64, i1)131declare void @llvm.memset.p5.i64(ptr addrspace(5), i8, i64, i1)132 133attributes #0 = { nounwind }134attributes #1 = { nounwind readnone }135