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1; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - -arm-atomic-cfg-tidy=0 | FileCheck %s2;3; LSR should only check for valid address modes when the IV user is a4; memory address.5; svn r158536, rdar://116359906;7; Note that we still don't produce the best code here because we fail8; to coalesce the IV. See <rdar://problem/11680670> [coalescer] IVs9; need to be scheduled to expose coalescing.10 11; LSR before the fix:12;The chosen solution requires 4 regs, with addrec cost 1, plus 3 base adds, plus 2 setup cost:13; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i3214; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>) + imm(1)15; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i3216; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>)17; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*18; reg((-4 + (4 * %v3) + %v1)) + 4*reg({0,+,-1}<%while.cond.i.i>)19; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*20; reg((-4 + (4 * %v3) + %v4)) + 4*reg({0,+,-1}<%while.cond.i.i>)21; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i3222; reg(%v3)23;24; LSR after the fix:25;The chosen solution requires 4 regs, with addrec cost 1, plus 1 base add, plus 2 setup cost:26; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i3227; reg({%v3,+,-1}<nsw><%while.cond.i.i>) + imm(1)28; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i3229; reg({%v3,+,-1}<nsw><%while.cond.i.i>)30; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*31; reg((-4 + %v1)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>)32; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*33; reg((-4 + %v4)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>)34; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i3235; reg(%v3)36 37 38%s = type { ptr }39 40@ncol = external global i32, align 441 42declare ptr @getptr() nounwind43declare ptr @getstruct() nounwind44 45; CHECK: @main46; Check that the loop preheader contains no address computation.47; CHECK: %while.cond.i.i48; CHECK-NOT: add{{.*}}lsl49; CHECK: ldr{{.*}}lsl #250; CHECK: ldr{{.*}}lsl #251define i32 @main() nounwind ssp {52entry:53 %v0 = load i32, ptr @ncol, align 454 %v1 = tail call ptr @getptr() nounwind55 %cmp10.i = icmp eq i32 %v0, 056 br label %while.cond.outer57 58while.cond.outer:59 %call18 = tail call ptr @getstruct() nounwind60 br label %while.cond61 62while.cond:63 %cmp20 = icmp eq ptr %v1, null64 br label %while.body65 66while.body:67 %v3 = load i32, ptr @ncol, align 468 br label %end_of_chain69 70end_of_chain:71 %v4 = load ptr, ptr %call18, align 472 br label %while.cond.i.i73 74while.cond.i.i:75 %counter.0.i.i = phi i32 [ %v3, %end_of_chain ], [ %dec.i.i, %land.rhs.i.i ]76 %dec.i.i = add nsw i32 %counter.0.i.i, -177 %tobool.i.i = icmp eq i32 %counter.0.i.i, 078 br i1 %tobool.i.i, label %where.exit, label %land.rhs.i.i79 80land.rhs.i.i:81 %arrayidx.i.i = getelementptr inbounds i32, ptr %v4, i32 %dec.i.i82 %v5 = load i32, ptr %arrayidx.i.i, align 483 %arrayidx1.i.i = getelementptr inbounds i32, ptr %v1, i32 %dec.i.i84 %v6 = load i32, ptr %arrayidx1.i.i, align 485 %cmp.i.i = icmp eq i32 %v5, %v686 br i1 %cmp.i.i, label %while.cond.i.i, label %equal_data.exit.i87 88equal_data.exit.i:89 ret i32 %counter.0.i.i90 91where.exit:92 br label %while.end.i93 94while.end.i:95 ret i32 %v396}97