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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt < %s -loop-reduce -S | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv6m-arm-none-eabi"6 7; These are regression tests for8; https://bugs.llvm.org/show_bug.cgi?id=341069; "ARMTargetLowering::isLegalAddressingMode can accept incorrect10; addressing modes for Thumb1 target"11; https://reviews.llvm.org/D3458312; "[LSR] Narrow search space by filtering non-optimal formulae with the13; same ScaledReg and Scale."14;15; Due to a bug in ARMTargetLowering::isLegalAddressingMode LSR got16; 4*reg({0,+,-1}) and -4*reg({0,+,-1}) had the same cost for the Thumb1 target.17; Another issue was that LSR got that -1*reg was free for the Thumb1 target.18 19; Test case 01: -1*reg is not free for the Thumb1 target.20define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n) nounwind {21; CHECK-LABEL: define ptr @negativeOneCase(22; CHECK-SAME: ptr returned [[A:%.*]], ptr readonly captures(none) [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {23; CHECK-NEXT: entry:24; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 -125; CHECK-NEXT: br label [[WHILE_COND:%.*]]26; CHECK: while.cond:27; CHECK-NEXT: [[P_0:%.*]] = phi ptr [ [[ADD_PTR]], [[ENTRY:%.*]] ], [ [[INCDEC_PTR:%.*]], [[WHILE_COND]] ]28; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr i8, ptr [[P_0]], i32 129; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[INCDEC_PTR]], align 130; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], 031; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_COND2_PREHEADER:%.*]], label [[WHILE_COND]]32; CHECK: while.cond2.preheader:33; CHECK-NEXT: br label [[WHILE_COND2:%.*]]34; CHECK: while.cond2:35; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[WHILE_BODY5:%.*]] ], [ 0, [[WHILE_COND2_PREHEADER]] ]36; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[B]], i32 [[LSR_IV]]37; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[INCDEC_PTR]], i32 [[LSR_IV]]38; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i32 [[N]], [[LSR_IV]]39; CHECK-NEXT: br i1 [[CMP3]], label [[WHILE_END8:%.*]], label [[WHILE_BODY5]]40; CHECK: while.body5:41; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SCEVGEP1]], align 142; CHECK-NEXT: store i8 [[TMP1]], ptr [[SCEVGEP2]], align 143; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 144; CHECK-NEXT: br label [[WHILE_COND2]]45; CHECK: while.end8:46; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[INCDEC_PTR]], i32 [[N]]47; CHECK-NEXT: store i8 0, ptr [[SCEVGEP]], align 148; CHECK-NEXT: ret ptr [[A]]49;50entry:51 %add.ptr = getelementptr inbounds i8, ptr %a, i32 -152 br label %while.cond53 54while.cond: ; preds = %while.cond, %entry55 %p.0 = phi ptr [ %add.ptr, %entry ], [ %incdec.ptr, %while.cond ]56 %incdec.ptr = getelementptr inbounds i8, ptr %p.0, i32 157 %0 = load i8, ptr %incdec.ptr, align 158 %cmp = icmp eq i8 %0, 059 br i1 %cmp, label %while.cond2.preheader, label %while.cond60 61while.cond2.preheader: ; preds = %while.cond62 br label %while.cond263 64while.cond2: ; preds = %while.cond2.preheader, %while.body565 %b.addr.0 = phi ptr [ %incdec.ptr6, %while.body5 ], [ %b, %while.cond2.preheader ]66 %n.addr.0 = phi i32 [ %dec, %while.body5 ], [ %n, %while.cond2.preheader ]67 %p.1 = phi ptr [ %incdec.ptr7, %while.body5 ], [ %incdec.ptr, %while.cond2.preheader ]68 %cmp3 = icmp eq i32 %n.addr.0, 069 br i1 %cmp3, label %while.end8, label %while.body570 71while.body5: ; preds = %while.cond272 %dec = add i32 %n.addr.0, -173 %incdec.ptr6 = getelementptr inbounds i8, ptr %b.addr.0, i32 174 %1 = load i8, ptr %b.addr.0, align 175 %incdec.ptr7 = getelementptr inbounds i8, ptr %p.1, i32 176 store i8 %1, ptr %p.1, align 177 br label %while.cond278 79while.end8: ; preds = %while.cond280 %scevgep = getelementptr i8, ptr %incdec.ptr, i32 %n81 store i8 0, ptr %scevgep, align 182 ret ptr %a83}84 85; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for86; the Thumb1 target.87define void @negativeFourCase(ptr %ptr1, ptr %ptr2) nounwind {88; CHECK-LABEL: define void @negativeFourCase(89; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] {90; CHECK-NEXT: entry:91; CHECK-NEXT: br label [[FOR_COND6_PREHEADER_US_I_I:%.*]]92; CHECK: for.cond6.preheader.us.i.i:93; CHECK-NEXT: [[ADDR_0108_US_I_I:%.*]] = phi ptr [ [[SCEVGEP_I_I:%.*]], [[IF_END48_US_I_I:%.*]] ], [ [[PTR1]], [[ENTRY:%.*]] ]94; CHECK-NEXT: [[INC49_US_I_I:%.*]] = phi i32 [ [[INC50_US_I_I:%.*]], [[IF_END48_US_I_I]] ], [ 0, [[ENTRY]] ]95; CHECK-NEXT: [[C1_0104_US_I_I:%.*]] = phi ptr [ [[C0_0103_US_I_I:%.*]], [[IF_END48_US_I_I]] ], [ [[PTR2]], [[ENTRY]] ]96; CHECK-NEXT: [[C0_0103_US_I_I]] = phi ptr [ [[C1_0104_US_I_I]], [[IF_END48_US_I_I]] ], [ [[PTR2]], [[ENTRY]] ]97; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[C1_0104_US_I_I]], i32 -498; CHECK-NEXT: br label [[FOR_BODY8_US_I_I:%.*]]99; CHECK: if.end48.us.i.i:100; CHECK-NEXT: [[SCEVGEP_I_I]] = getelementptr i8, ptr [[ADDR_0108_US_I_I]], i32 256101; CHECK-NEXT: [[INC50_US_I_I]] = add nuw nsw i32 [[INC49_US_I_I]], 1102; CHECK-NEXT: [[EXITCOND110_I_I:%.*]] = icmp eq i32 [[INC50_US_I_I]], 256103; CHECK-NEXT: br i1 [[EXITCOND110_I_I]], label [[EXIT_I:%.*]], label [[FOR_COND6_PREHEADER_US_I_I]]104; CHECK: for.body8.us.i.i:105; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[FOR_INC_US_I_I:%.*]] ], [ 0, [[FOR_COND6_PREHEADER_US_I_I]] ]106; CHECK-NEXT: [[ADDR_198_US_I_I:%.*]] = phi ptr [ [[ADDR_0108_US_I_I]], [[FOR_COND6_PREHEADER_US_I_I]] ], [ [[INCDEC_PTR_US_I_I:%.*]], [[FOR_INC_US_I_I]] ]107; CHECK-NEXT: [[INC_196_US_I_I:%.*]] = phi i32 [ 0, [[FOR_COND6_PREHEADER_US_I_I]] ], [ [[INC_2_US_I_I:%.*]], [[FOR_INC_US_I_I]] ]108; CHECK-NEXT: [[INCDEC_PTR_US_I_I]] = getelementptr inbounds i8, ptr [[ADDR_198_US_I_I]], i32 1109; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ADDR_198_US_I_I]], align 1110; CHECK-NEXT: [[CMP9_US_I_I:%.*]] = icmp eq i8 [[TMP0]], -1111; CHECK-NEXT: br i1 [[CMP9_US_I_I]], label [[IF_END37_US_I_I:%.*]], label [[IF_ELSE_US_I_I:%.*]]112; CHECK: if.else.us.i.i:113; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[C1_0104_US_I_I]], i32 [[LSR_IV]]114; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i32 4115; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[SCEVGEP5]], align 4116; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[C1_0104_US_I_I]], i32 [[LSR_IV]]117; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[SCEVGEP3]], align 4118; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i32 [[LSR_IV]]119; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SCEVGEP2]], align 4120; CHECK-NEXT: br label [[IF_END37_US_I_I]]121; CHECK: if.end37.us.i.i:122; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP3]], [[IF_ELSE_US_I_I]] ], [ 0, [[FOR_BODY8_US_I_I]] ]123; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[C0_0103_US_I_I]], i32 [[LSR_IV]]124; CHECK-NEXT: store i32 [[TMP4]], ptr [[SCEVGEP]], align 4125; CHECK-NEXT: [[INC_US_I_I:%.*]] = add nsw i32 [[INC_196_US_I_I]], 1126; CHECK-NEXT: [[CMP38_US_I_I:%.*]] = icmp sgt i32 [[INC_196_US_I_I]], 6127; CHECK-NEXT: br i1 [[CMP38_US_I_I]], label [[IF_THEN40_US_I_I:%.*]], label [[FOR_INC_US_I_I]]128; CHECK: if.then40.us.i.i:129; CHECK-NEXT: br label [[FOR_INC_US_I_I]]130; CHECK: for.inc.us.i.i:131; CHECK-NEXT: [[INC_2_US_I_I]] = phi i32 [ 0, [[IF_THEN40_US_I_I]] ], [ [[INC_US_I_I]], [[IF_END37_US_I_I]] ]132; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 4133; CHECK-NEXT: [[EXITCOND_I_I:%.*]] = icmp eq i32 1024, [[LSR_IV_NEXT]]134; CHECK-NEXT: br i1 [[EXITCOND_I_I]], label [[IF_END48_US_I_I]], label [[FOR_BODY8_US_I_I]]135; CHECK: exit.i:136; CHECK-NEXT: ret void137;138entry:139 br label %for.cond6.preheader.us.i.i140 141for.cond6.preheader.us.i.i: ; preds = %if.end48.us.i.i, %entry142 %addr.0108.us.i.i = phi ptr [ %scevgep.i.i, %if.end48.us.i.i ], [ %ptr1, %entry ]143 %inc49.us.i.i = phi i32 [ %inc50.us.i.i, %if.end48.us.i.i ], [ 0, %entry ]144 %c1.0104.us.i.i = phi ptr [ %c0.0103.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]145 %c0.0103.us.i.i = phi ptr [ %c1.0104.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]146 br label %for.body8.us.i.i147 148if.end48.us.i.i: ; preds = %for.inc.us.i.i149 %scevgep.i.i = getelementptr i8, ptr %addr.0108.us.i.i, i32 256150 %inc50.us.i.i = add nuw nsw i32 %inc49.us.i.i, 1151 %exitcond110.i.i = icmp eq i32 %inc50.us.i.i, 256152 br i1 %exitcond110.i.i, label %exit.i, label %for.cond6.preheader.us.i.i153 154for.body8.us.i.i: ; preds = %for.inc.us.i.i, %for.cond6.preheader.us.i.i155 %addr.198.us.i.i = phi ptr [ %addr.0108.us.i.i, %for.cond6.preheader.us.i.i ], [ %incdec.ptr.us.i.i, %for.inc.us.i.i ]156 %inc.196.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc.2.us.i.i, %for.inc.us.i.i ]157 %c.093.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc43.us.i.i, %for.inc.us.i.i ]158 %incdec.ptr.us.i.i = getelementptr inbounds i8, ptr %addr.198.us.i.i, i32 1159 %0 = load i8, ptr %addr.198.us.i.i, align 1160 %cmp9.us.i.i = icmp eq i8 %0, -1161 br i1 %cmp9.us.i.i, label %if.end37.us.i.i, label %if.else.us.i.i162 163if.else.us.i.i: ; preds = %for.body8.us.i.i164 %add12.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1165 %arrayidx13.us.i.i = getelementptr inbounds i32, ptr %c1.0104.us.i.i, i32 %add12.us.i.i166 %1 = load i32, ptr %arrayidx13.us.i.i, align 4167 %arrayidx16.us.i.i = getelementptr inbounds i32, ptr %c1.0104.us.i.i, i32 %c.093.us.i.i168 %2 = load i32, ptr %arrayidx16.us.i.i, align 4169 %sub19.us.i.i = add nsw i32 %c.093.us.i.i, -1170 %arrayidx20.us.i.i = getelementptr inbounds i32, ptr %c1.0104.us.i.i, i32 %sub19.us.i.i171 %3 = load i32, ptr %arrayidx20.us.i.i, align 4172 br label %if.end37.us.i.i173 174if.end37.us.i.i: ; preds = %if.else.us.i.i, %for.body8.us.i.i175 %4 = phi i32 [ %3, %if.else.us.i.i ], [ 0, %for.body8.us.i.i ]176 %arrayidx36.us.i.i = getelementptr inbounds i32, ptr %c0.0103.us.i.i, i32 %c.093.us.i.i177 store i32 %4, ptr %arrayidx36.us.i.i, align 4178 %inc.us.i.i = add nsw i32 %inc.196.us.i.i, 1179 %cmp38.us.i.i = icmp sgt i32 %inc.196.us.i.i, 6180 br i1 %cmp38.us.i.i, label %if.then40.us.i.i, label %for.inc.us.i.i181 182if.then40.us.i.i: ; preds = %if.end37.us.i.i183 br label %for.inc.us.i.i184 185for.inc.us.i.i: ; preds = %if.then40.us.i.i, %if.end37.us.i.i186 %inc.2.us.i.i = phi i32 [ 0, %if.then40.us.i.i ], [ %inc.us.i.i, %if.end37.us.i.i ]187 %inc43.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1188 %exitcond.i.i = icmp eq i32 %inc43.us.i.i, 256189 br i1 %exitcond.i.i, label %if.end48.us.i.i, label %for.body8.us.i.i190 191exit.i: ; preds = %if.end48.us.i.i192 ret void193}194 195