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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A93 4; @simple is the most basic chain of address induction variables. Chaining5; saves at least one register and avoids complex addressing and setup6; code.7;8; no expensive address computation in the preheader9; no complex address modes10define i32 @simple(ptr %a, ptr %b, i32 %x) nounwind {11; A9-LABEL: simple:12; A9: @ %bb.0: @ %entry13; A9-NEXT: .save {r4, r5, r6, lr}14; A9-NEXT: push {r4, r5, r6, lr}15; A9-NEXT: mov r3, r016; A9-NEXT: lsls r2, r2, #217; A9-NEXT: movs r0, #018; A9-NEXT: .LBB0_1: @ %loop19; A9-NEXT: @ =>This Inner Loop Header: Depth=120; A9-NEXT: add.w lr, r3, r221; A9-NEXT: ldr.w r12, [r3, r2]22; A9-NEXT: ldr r3, [r3]23; A9-NEXT: add.w r4, lr, r224; A9-NEXT: ldr.w r6, [lr, r2]25; A9-NEXT: add r0, r326; A9-NEXT: ldr r5, [r4, r2]27; A9-NEXT: add r0, r1228; A9-NEXT: adds r3, r4, r229; A9-NEXT: add r0, r630; A9-NEXT: add r3, r231; A9-NEXT: add r0, r532; A9-NEXT: cmp r3, r133; A9-NEXT: bne .LBB0_134; A9-NEXT: @ %bb.2: @ %exit35; A9-NEXT: pop {r4, r5, r6, pc}36entry:37 br label %loop38loop:39 %iv = phi ptr [ %a, %entry ], [ %iv4, %loop ]40 %s = phi i32 [ 0, %entry ], [ %s4, %loop ]41 %v = load i32, ptr %iv42 %iv1 = getelementptr inbounds i32, ptr %iv, i32 %x43 %v1 = load i32, ptr %iv144 %iv2 = getelementptr inbounds i32, ptr %iv1, i32 %x45 %v2 = load i32, ptr %iv246 %iv3 = getelementptr inbounds i32, ptr %iv2, i32 %x47 %v3 = load i32, ptr %iv348 %s1 = add i32 %s, %v49 %s2 = add i32 %s1, %v150 %s3 = add i32 %s2, %v251 %s4 = add i32 %s3, %v352 %iv4 = getelementptr inbounds i32, ptr %iv3, i32 %x53 %cmp = icmp eq ptr %iv4, %b54 br i1 %cmp, label %exit, label %loop55exit:56 ret i32 %s457}58 59; @user is not currently chained because the IV is live across memory ops.60;61; stride multiples computed in the preheader62; complex address modes63define i32 @user(ptr %a, ptr %b, i32 %x) nounwind {64; A9-LABEL: user:65; A9: @ %bb.0: @ %entry66; A9-NEXT: .save {r4, r5, r6, r7, lr}67; A9-NEXT: push {r4, r5, r6, r7, lr}68; A9-NEXT: add.w r3, r2, r2, lsl #169; A9-NEXT: lsl.w r12, r2, #470; A9-NEXT: lsl.w lr, r3, #271; A9-NEXT: movs r3, #072; A9-NEXT: .LBB1_1: @ %loop73; A9-NEXT: @ =>This Inner Loop Header: Depth=174; A9-NEXT: ldr r4, [r0]75; A9-NEXT: ldr.w r5, [r0, r2, lsl #3]76; A9-NEXT: ldr.w r6, [r0, r2, lsl #2]77; A9-NEXT: add r3, r478; A9-NEXT: ldr.w r7, [r0, lr]79; A9-NEXT: add r3, r680; A9-NEXT: add r3, r581; A9-NEXT: add r3, r782; A9-NEXT: str r3, [r0]83; A9-NEXT: add r0, r1284; A9-NEXT: cmp r0, r185; A9-NEXT: bne .LBB1_186; A9-NEXT: @ %bb.2: @ %exit87; A9-NEXT: mov r0, r388; A9-NEXT: pop {r4, r5, r6, r7, pc}89entry:90 br label %loop91loop:92 %iv = phi ptr [ %a, %entry ], [ %iv4, %loop ]93 %s = phi i32 [ 0, %entry ], [ %s4, %loop ]94 %v = load i32, ptr %iv95 %iv1 = getelementptr inbounds i32, ptr %iv, i32 %x96 %v1 = load i32, ptr %iv197 %iv2 = getelementptr inbounds i32, ptr %iv1, i32 %x98 %v2 = load i32, ptr %iv299 %iv3 = getelementptr inbounds i32, ptr %iv2, i32 %x100 %v3 = load i32, ptr %iv3101 %s1 = add i32 %s, %v102 %s2 = add i32 %s1, %v1103 %s3 = add i32 %s2, %v2104 %s4 = add i32 %s3, %v3105 %iv4 = getelementptr inbounds i32, ptr %iv3, i32 %x106 store i32 %s4, ptr %iv107 %cmp = icmp eq ptr %iv4, %b108 br i1 %cmp, label %exit, label %loop109exit:110 ret i32 %s4111}112 113; @extrastride is a slightly more interesting case of a single114; complete chain with multiple strides. The test case IR is what LSR115; used to do, and exactly what we don't want to do. LSR's new IV116; chaining feature should now undo the damage.117;118; no spills119; only one stride multiple in the preheader120; no complex address modes or reloads121define void @extrastride(ptr nocapture %main, i32 %main_stride, ptr nocapture %res, i32 %x, i32 %y, i32 %z) nounwind {122; A9-LABEL: extrastride:123; A9: @ %bb.0: @ %entry124; A9-NEXT: .save {r4, r5, r6, r7, lr}125; A9-NEXT: push {r4, r5, r6, r7, lr}126; A9-NEXT: ldr.w r12, [sp, #24]127; A9-NEXT: cmp.w r12, #0128; A9-NEXT: beq .LBB2_3129; A9-NEXT: @ %bb.1: @ %for.body.lr.ph130; A9-NEXT: ldr r4, [sp, #20]131; A9-NEXT: add.w lr, r3, r1132; A9-NEXT: lsls r3, r4, #2133; A9-NEXT: .LBB2_2: @ %for.body134; A9-NEXT: @ =>This Inner Loop Header: Depth=1135; A9-NEXT: adds r5, r0, r1136; A9-NEXT: ldr r4, [r0, r1]137; A9-NEXT: ldr r0, [r0]138; A9-NEXT: subs.w r12, r12, #1139; A9-NEXT: ldr r6, [r5, r1]140; A9-NEXT: add r5, r1141; A9-NEXT: add r0, r4142; A9-NEXT: ldr r7, [r5, r1]143; A9-NEXT: add r5, r1144; A9-NEXT: add r0, r6145; A9-NEXT: ldr r4, [r5, r1]146; A9-NEXT: add r0, r7147; A9-NEXT: add r0, r4148; A9-NEXT: str r0, [r2]149; A9-NEXT: add.w r0, r5, r1150; A9-NEXT: add r2, r3151; A9-NEXT: add r0, lr152; A9-NEXT: bne .LBB2_2153; A9-NEXT: .LBB2_3: @ %for.end154; A9-NEXT: pop {r4, r5, r6, r7, pc}155entry:156 %cmp8 = icmp eq i32 %z, 0157 br i1 %cmp8, label %for.end, label %for.body.lr.ph158 159for.body.lr.ph: ; preds = %entry160 %add.ptr.sum = shl i32 %main_stride, 1 ; s*2161 %add.ptr1.sum = add i32 %add.ptr.sum, %main_stride ; s*3162 %add.ptr2.sum = add i32 %x, %main_stride ; s + x163 %add.ptr4.sum = shl i32 %main_stride, 2 ; s*4164 %add.ptr3.sum = add i32 %add.ptr2.sum, %add.ptr4.sum ; total IV stride = s*5+x165 br label %for.body166 167for.body: ; preds = %for.body.lr.ph, %for.body168 %main.addr.011 = phi ptr [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]169 %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]170 %res.addr.09 = phi ptr [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ]171 %0 = load i32, ptr %main.addr.011, align 4172 %add.ptr = getelementptr inbounds i8, ptr %main.addr.011, i32 %main_stride173 %1 = load i32, ptr %add.ptr, align 4174 %add.ptr1 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr.sum175 %2 = load i32, ptr %add.ptr1, align 4176 %add.ptr2 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr1.sum177 %3 = load i32, ptr %add.ptr2, align 4178 %add.ptr3 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr4.sum179 %4 = load i32, ptr %add.ptr3, align 4180 %add = add i32 %1, %0181 %add4 = add i32 %add, %2182 %add5 = add i32 %add4, %3183 %add6 = add i32 %add5, %4184 store i32 %add6, ptr %res.addr.09, align 4185 %add.ptr6 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr3.sum186 %add.ptr7 = getelementptr inbounds i32, ptr %res.addr.09, i32 %y187 %inc = add i32 %i.010, 1188 %cmp = icmp eq i32 %inc, %z189 br i1 %cmp, label %for.end, label %for.body190 191for.end: ; preds = %for.body, %entry192 ret void193}194 195; @foldedidx is an unrolled variant of this loop:196; for (unsigned long i = 0; i < len; i += s) {197; c[i] = a[i] + b[i];198; }199; where 's' can be folded into the addressing mode.200; Consequently, we should *not* form any chains.201define void @foldedidx(ptr nocapture %a, ptr nocapture %b, ptr nocapture %c) nounwind ssp {202; A9-LABEL: foldedidx:203; A9: @ %bb.0: @ %entry204; A9-NEXT: .save {r4, r5, r6, lr}205; A9-NEXT: push {r4, r5, r6, lr}206; A9-NEXT: mov.w lr, #0207; A9-NEXT: .LBB3_1: @ %for.body208; A9-NEXT: @ =>This Inner Loop Header: Depth=1209; A9-NEXT: ldrb.w r12, [r0, lr]210; A9-NEXT: add.w r4, r1, lr211; A9-NEXT: ldrb.w r3, [r1, lr]212; A9-NEXT: add r3, r12213; A9-NEXT: strb.w r3, [r2, lr]214; A9-NEXT: add.w r3, r0, lr215; A9-NEXT: ldrb.w r12, [r3, #1]216; A9-NEXT: ldrb r5, [r4, #1]217; A9-NEXT: add r12, r5218; A9-NEXT: add.w r5, r2, lr219; A9-NEXT: strb.w r12, [r5, #1]220; A9-NEXT: add.w lr, lr, #4221; A9-NEXT: cmp.w lr, #400222; A9-NEXT: ldrb.w r12, [r3, #2]223; A9-NEXT: ldrb r6, [r4, #2]224; A9-NEXT: add r6, r12225; A9-NEXT: strb r6, [r5, #2]226; A9-NEXT: ldrb r3, [r3, #3]227; A9-NEXT: ldrb r6, [r4, #3]228; A9-NEXT: add r3, r6229; A9-NEXT: strb r3, [r5, #3]230; A9-NEXT: bne .LBB3_1231; A9-NEXT: @ %bb.2: @ %for.end232; A9-NEXT: pop {r4, r5, r6, pc}233entry:234 br label %for.body235 236for.body: ; preds = %for.body, %entry237 %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ]238 %arrayidx = getelementptr inbounds i8, ptr %a, i32 %i.07239 %0 = load i8, ptr %arrayidx, align 1240 %conv5 = zext i8 %0 to i32241 %arrayidx1 = getelementptr inbounds i8, ptr %b, i32 %i.07242 %1 = load i8, ptr %arrayidx1, align 1243 %conv26 = zext i8 %1 to i32244 %add = add nsw i32 %conv26, %conv5245 %conv3 = trunc i32 %add to i8246 %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.07247 store i8 %conv3, ptr %arrayidx4, align 1248 %inc1 = or disjoint i32 %i.07, 1249 %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %inc1250 %2 = load i8, ptr %arrayidx.1, align 1251 %conv5.1 = zext i8 %2 to i32252 %arrayidx1.1 = getelementptr inbounds i8, ptr %b, i32 %inc1253 %3 = load i8, ptr %arrayidx1.1, align 1254 %conv26.1 = zext i8 %3 to i32255 %add.1 = add nsw i32 %conv26.1, %conv5.1256 %conv3.1 = trunc i32 %add.1 to i8257 %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %inc1258 store i8 %conv3.1, ptr %arrayidx4.1, align 1259 %inc.12 = or disjoint i32 %i.07, 2260 %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %inc.12261 %4 = load i8, ptr %arrayidx.2, align 1262 %conv5.2 = zext i8 %4 to i32263 %arrayidx1.2 = getelementptr inbounds i8, ptr %b, i32 %inc.12264 %5 = load i8, ptr %arrayidx1.2, align 1265 %conv26.2 = zext i8 %5 to i32266 %add.2 = add nsw i32 %conv26.2, %conv5.2267 %conv3.2 = trunc i32 %add.2 to i8268 %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %inc.12269 store i8 %conv3.2, ptr %arrayidx4.2, align 1270 %inc.23 = or disjoint i32 %i.07, 3271 %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %inc.23272 %6 = load i8, ptr %arrayidx.3, align 1273 %conv5.3 = zext i8 %6 to i32274 %arrayidx1.3 = getelementptr inbounds i8, ptr %b, i32 %inc.23275 %7 = load i8, ptr %arrayidx1.3, align 1276 %conv26.3 = zext i8 %7 to i32277 %add.3 = add nsw i32 %conv26.3, %conv5.3278 %conv3.3 = trunc i32 %add.3 to i8279 %arrayidx4.3 = getelementptr inbounds i8, ptr %c, i32 %inc.23280 store i8 %conv3.3, ptr %arrayidx4.3, align 1281 %inc.3 = add nsw i32 %i.07, 4282 %exitcond.3 = icmp eq i32 %inc.3, 400283 br i1 %exitcond.3, label %for.end, label %for.body284 285for.end: ; preds = %for.body286 ret void287}288 289; @testNeon is an important example of the nead for ivchains.290;291; Loads and stores should use post-increment addressing, no add's or add.w's.292; Most importantly, there should be no spills or reloads!293define hidden void @testNeon(ptr %ref_data, i32 %ref_stride, i32 %limit, ptr nocapture %data) nounwind optsize {294; A9-LABEL: testNeon:295; A9: @ %bb.0:296; A9-NEXT: .save {r4, r5, r7, lr}297; A9-NEXT: push {r4, r5, r7, lr}298; A9-NEXT: vmov.i32 q8, #0x0299; A9-NEXT: cmp r2, #1300; A9-NEXT: blt .LBB4_4301; A9-NEXT: @ %bb.1: @ %.lr.ph302; A9-NEXT: movs r5, #0303; A9-NEXT: movw r4, #64464304; A9-NEXT: sub.w r12, r5, r2, lsl #6305; A9-NEXT: sub.w lr, r1, r1, lsl #4306; A9-NEXT: movt r4, #65535307; A9-NEXT: mov r5, r3308; A9-NEXT: .LBB4_2: @ =>This Inner Loop Header: Depth=1309; A9-NEXT: vld1.64 {d18}, [r0], r1310; A9-NEXT: subs r2, #1311; A9-NEXT: vld1.64 {d19}, [r0], r1312; A9-NEXT: vst1.8 {d18, d19}, [r5]!313; A9-NEXT: vld1.64 {d20}, [r0], r1314; A9-NEXT: vld1.64 {d21}, [r0], r1315; A9-NEXT: vst1.8 {d20, d21}, [r5]!316; A9-NEXT: vld1.64 {d22}, [r0], r1317; A9-NEXT: vadd.i8 q9, q9, q10318; A9-NEXT: vld1.64 {d23}, [r0], r1319; A9-NEXT: vst1.8 {d22, d23}, [r5]!320; A9-NEXT: vld1.64 {d20}, [r0], r1321; A9-NEXT: vadd.i8 q9, q9, q11322; A9-NEXT: vld1.64 {d21}, [r0], lr323; A9-NEXT: vadd.i8 q9, q9, q10324; A9-NEXT: vadd.i8 q8, q8, q9325; A9-NEXT: vst1.8 {d20, d21}, [r5], r4326; A9-NEXT: bne .LBB4_2327; A9-NEXT: @ %bb.3: @ %._crit_edge328; A9-NEXT: add.w r3, r3, r12, lsl #4329; A9-NEXT: .LBB4_4:330; A9-NEXT: vst1.32 {d16, d17}, [r3]331; A9-NEXT: pop {r4, r5, r7, pc}332 %1 = icmp sgt i32 %limit, 0333 br i1 %1, label %.lr.ph, label %45334 335.lr.ph: ; preds = %0336 %2 = shl nsw i32 %ref_stride, 1337 %3 = mul nsw i32 %ref_stride, 3338 %4 = shl nsw i32 %ref_stride, 2339 %5 = mul nsw i32 %ref_stride, 5340 %6 = mul nsw i32 %ref_stride, 6341 %7 = mul nsw i32 %ref_stride, 7342 %8 = shl nsw i32 %ref_stride, 3343 %9 = sub i32 0, %8344 %10 = mul i32 %limit, -64345 br label %11346 347; <label>:11 ; preds = %11, %.lr.ph348 %.05 = phi ptr [ %ref_data, %.lr.ph ], [ %42, %11 ]349 %counter.04 = phi i32 [ 0, %.lr.ph ], [ %44, %11 ]350 %result.03 = phi <16 x i8> [ zeroinitializer, %.lr.ph ], [ %41, %11 ]351 %.012 = phi ptr [ %data, %.lr.ph ], [ %43, %11 ]352 %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %.05, i32 1) nounwind353 %13 = getelementptr inbounds i8, ptr %.05, i32 %ref_stride354 %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %13, i32 1) nounwind355 %15 = shufflevector <1 x i64> %12, <1 x i64> %14, <2 x i32> <i32 0, i32 1>356 %16 = bitcast <2 x i64> %15 to <16 x i8>357 %17 = getelementptr inbounds <16 x i8>, ptr %.012, i32 1358 store <16 x i8> %16, ptr %.012, align 4359 %18 = getelementptr inbounds i8, ptr %.05, i32 %2360 %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %18, i32 1) nounwind361 %20 = getelementptr inbounds i8, ptr %.05, i32 %3362 %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %20, i32 1) nounwind363 %22 = shufflevector <1 x i64> %19, <1 x i64> %21, <2 x i32> <i32 0, i32 1>364 %23 = bitcast <2 x i64> %22 to <16 x i8>365 %24 = getelementptr inbounds <16 x i8>, ptr %.012, i32 2366 store <16 x i8> %23, ptr %17, align 4367 %25 = getelementptr inbounds i8, ptr %.05, i32 %4368 %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %25, i32 1) nounwind369 %27 = getelementptr inbounds i8, ptr %.05, i32 %5370 %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %27, i32 1) nounwind371 %29 = shufflevector <1 x i64> %26, <1 x i64> %28, <2 x i32> <i32 0, i32 1>372 %30 = bitcast <2 x i64> %29 to <16 x i8>373 %31 = getelementptr inbounds <16 x i8>, ptr %.012, i32 3374 store <16 x i8> %30, ptr %24, align 4375 %32 = getelementptr inbounds i8, ptr %.05, i32 %6376 %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %32, i32 1) nounwind377 %34 = getelementptr inbounds i8, ptr %.05, i32 %7378 %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %34, i32 1) nounwind379 %36 = shufflevector <1 x i64> %33, <1 x i64> %35, <2 x i32> <i32 0, i32 1>380 %37 = bitcast <2 x i64> %36 to <16 x i8>381 store <16 x i8> %37, ptr %31, align 4382 %38 = add <16 x i8> %16, %23383 %39 = add <16 x i8> %38, %30384 %40 = add <16 x i8> %39, %37385 %41 = add <16 x i8> %result.03, %40386 %42 = getelementptr i8, ptr %.05, i32 %9387 %43 = getelementptr inbounds <16 x i8>, ptr %.012, i32 -64388 %44 = add nsw i32 %counter.04, 1389 %exitcond = icmp eq i32 %44, %limit390 br i1 %exitcond, label %._crit_edge, label %11391 392._crit_edge: ; preds = %11393 %scevgep = getelementptr <16 x i8>, ptr %data, i32 %10394 br label %45395 396; <label>:45 ; preds = %._crit_edge, %0397 %result.0.lcssa = phi <16 x i8> [ %41, %._crit_edge ], [ zeroinitializer, %0 ]398 %.01.lcssa = phi ptr [ %scevgep, %._crit_edge ], [ %data, %0 ]399 store <16 x i8> %result.0.lcssa, ptr %.01.lcssa, align 4400 ret void401}402 403declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr, i32) nounwind readonly404 405; Handle chains in which the same offset is used for both loads and406; stores to the same array.407; rdar://11410078.408define void @testReuse(ptr %src, i32 %stride) nounwind ssp {409; A9-LABEL: testReuse:410; A9: @ %bb.0: @ %entry411; A9-NEXT: sub.w r12, r0, r1, lsl #2412; A9-NEXT: sub.w r0, r1, r1, lsl #2413; A9-NEXT: lsls r2, r0, #1414; A9-NEXT: movs r3, #0415; A9-NEXT: .LBB5_1: @ %for.body416; A9-NEXT: @ =>This Inner Loop Header: Depth=1417; A9-NEXT: add.w r0, r12, r3418; A9-NEXT: adds r3, #8419; A9-NEXT: vld1.8 {d16}, [r0], r1420; A9-NEXT: cmp r3, #32421; A9-NEXT: vld1.8 {d17}, [r0], r1422; A9-NEXT: vhadd.u8 d16, d16, d17423; A9-NEXT: vld1.8 {d18}, [r0], r1424; A9-NEXT: vhadd.u8 d17, d17, d18425; A9-NEXT: vld1.8 {d19}, [r0], r1426; A9-NEXT: vhadd.u8 d18, d18, d19427; A9-NEXT: vld1.8 {d20}, [r0], r1428; A9-NEXT: vhadd.u8 d19, d19, d20429; A9-NEXT: vld1.8 {d21}, [r0], r1430; A9-NEXT: vhadd.u8 d20, d20, d21431; A9-NEXT: vld1.8 {d22}, [r0], r1432; A9-NEXT: vhadd.u8 d21, d21, d22433; A9-NEXT: vld1.8 {d23}, [r0], r2434; A9-NEXT: vst1.8 {d16}, [r0], r1435; A9-NEXT: vst1.8 {d17}, [r0], r1436; A9-NEXT: vst1.8 {d18}, [r0], r1437; A9-NEXT: vst1.8 {d19}, [r0], r1438; A9-NEXT: vst1.8 {d20}, [r0], r1439; A9-NEXT: vst1.8 {d21}, [r0]440; A9-NEXT: bne .LBB5_1441; A9-NEXT: @ %bb.2: @ %for.end442; A9-NEXT: bx lr443entry:444 %mul = shl nsw i32 %stride, 2445 %idx.neg = sub i32 0, %mul446 %mul1 = mul nsw i32 %stride, 3447 %idx.neg2 = sub i32 0, %mul1448 %mul5 = shl nsw i32 %stride, 1449 %idx.neg6 = sub i32 0, %mul5450 %idx.neg10 = sub i32 0, %stride451 br label %for.body452 453for.body: ; preds = %for.body, %entry454 %i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ]455 %src.addr = phi ptr [ %src, %entry ], [ %add.ptr45, %for.body ]456 %add.ptr = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg457 %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr, i32 1)458 %add.ptr3 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg2459 %vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr3, i32 1)460 %add.ptr7 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg6461 %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr7, i32 1)462 %add.ptr11 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg10463 %vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr11, i32 1)464 %vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %src.addr, i32 1)465 %add.ptr17 = getelementptr inbounds i8, ptr %src.addr, i32 %stride466 %vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr17, i32 1)467 %add.ptr20 = getelementptr inbounds i8, ptr %src.addr, i32 %mul5468 %vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr20, i32 1)469 %add.ptr23 = getelementptr inbounds i8, ptr %src.addr, i32 %mul1470 %vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr23, i32 1)471 %vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind472 %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind473 %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind474 %vadd4 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld4, <8 x i8> %vld5) nounwind475 %vadd5 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld5, <8 x i8> %vld6) nounwind476 %vadd6 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld6, <8 x i8> %vld7) nounwind477 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr3, <8 x i8> %vadd1, i32 1)478 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr7, <8 x i8> %vadd2, i32 1)479 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr11, <8 x i8> %vadd3, i32 1)480 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %src.addr, <8 x i8> %vadd4, i32 1)481 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr17, <8 x i8> %vadd5, i32 1)482 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr20, <8 x i8> %vadd6, i32 1)483 %inc = add nsw i32 %i.0110, 1484 %add.ptr45 = getelementptr inbounds i8, ptr %src.addr, i32 8485 %exitcond = icmp eq i32 %inc, 4486 br i1 %exitcond, label %for.end, label %for.body487 488for.end: ; preds = %for.body489 ret void490}491 492declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr, i32) nounwind readonly493 494declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind495 496declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone497