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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; REQUIRES: x86-registered-target3; RUN: opt -loop-reduce -S < %s | FileCheck %s4 5; Strength reduction analysis here relies on IV Users analysis, that6; only finds users among instructions with types that are treated as7; legal by the data layout. When running this test on pure non-x868; configs (for example, ARM 64), it gets confused with the target9; triple and uses a default data layout instead. This default layout10; does not have any legal types (even i32), so the transformation11; does not happen.12 13target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"14target triple = "x86_64-apple-macosx"15 16; PR15470: LSR miscompile. The test2 function should return '1'.17;18; SCEV expander cannot expand quadratic recurrences outside of the19; loop. This recurrence depends on %sub.us, so can't be expanded.20; We cannot fold SCEVUnknown (sub.us) with recurrences since it is21; declared after the loop.22define i32 @test2(i32 %a, i32 %b) {23; CHECK-LABEL: @test2(24; CHECK-NEXT: entry:25; CHECK-NEXT: br label [[TEST2_LOOP:%.*]]26; CHECK: test2.loop:27; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[TEST2_LOOP]] ], [ -16777216, [[ENTRY:%.*]] ]28; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[TEST2_LOOP]] ], [ 1, [[ENTRY]] ]29; CHECK-NEXT: [[INC1115_US:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC11_US:%.*]], [[TEST2_LOOP]] ]30; CHECK-NEXT: [[INC11_US]] = add nsw i32 [[INC1115_US]], 131; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -132; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i32 [[LSR_IV1]], 1677721633; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i32 [[INC11_US]], 234; CHECK-NEXT: br i1 [[CMP_US]], label [[TEST2_LOOP]], label [[FOR_END:%.*]]35; CHECK: for.end:36; CHECK-NEXT: [[TOBOOL_US:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 037; CHECK-NEXT: [[SUB_US:%.*]] = select i1 [[TOBOOL_US]], i32 [[A:%.*]], i32 [[B:%.*]]38; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[SUB_US]]39; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[LSR_IV_NEXT]]40; CHECK-NEXT: [[SEXT_US:%.*]] = mul i32 [[LSR_IV_NEXT2]], [[TMP1]]41; CHECK-NEXT: [[F:%.*]] = ashr i32 [[SEXT_US]], 2442; CHECK-NEXT: br label [[EXIT:%.*]]43; CHECK: exit:44; CHECK-NEXT: ret i32 [[F]]45;46entry:47 br label %test2.loop48 49test2.loop:50 %inc1115.us = phi i32 [ 0, %entry ], [ %inc11.us, %test2.loop ]51 %inc11.us = add nsw i32 %inc1115.us, 152 %cmp.us = icmp slt i32 %inc11.us, 253 br i1 %cmp.us, label %test2.loop, label %for.end54 55for.end:56 %tobool.us = icmp eq i32 %inc1115.us, 057 %sub.us = select i1 %tobool.us, i32 %a, i32 %b58 %mul.us = shl i32 %inc1115.us, 2459 %sub.cond.us = sub nsw i32 %inc1115.us, %sub.us60 %sext.us = mul i32 %mul.us, %sub.cond.us61 %f = ashr i32 %sext.us, 2462 br label %exit63 64exit:65 ret i32 %f66}67