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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -loop-reduce -S %s | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-apple-macosx"6 7declare void @use(i64)8declare void @use.i32(i32)9declare void @use.i8(i8)10 11define i32 @test_pr38847() {12; CHECK-LABEL: define i32 @test_pr38847() {13; CHECK-NEXT: entry:14; CHECK-NEXT: br label [[LOOP:%.*]]15; CHECK: loop:16; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[LOOP]] ], [ 1, [[ENTRY:%.*]] ]17; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 1, [[ENTRY]] ]18; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i32 [[LSR_IV1]], -119; CHECK-NEXT: [[LSR:%.*]] = trunc i32 [[LSR_IV_NEXT2]] to i820; CHECK-NEXT: call void @use(i64 [[LSR_IV]])21; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -122; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i8 [[LSR]], -123; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT:%.*]]24; CHECK: exit:25; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[LSR_IV_NEXT2]], 926; CHECK-NEXT: ret i32 [[TMP2]]27;28entry:29 br label %loop30 31loop:32 %iv = phi i8 [ 1, %entry ], [ %iv.next, %loop ]33 %iv.next = add nsw i8 %iv, -134 %ext = zext i8 %iv to i6435 call void @use(i64 %ext)36 %cmp2 = icmp sgt i8 %iv.next, -137 br i1 %cmp2, label %loop, label %exit38 39exit:40 %sext = sext i8 %iv.next to i3241 %rem = urem i32 %sext, 942 ret i32 %rem43}44 45define i64 @test_pr58039() {46; CHECK-LABEL: define i64 @test_pr58039() {47; CHECK-NEXT: entry:48; CHECK-NEXT: br label [[LOOP:%.*]]49; CHECK: loop:50; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ -4294967213, [[ENTRY:%.*]] ]51; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]52; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[IV]] to i3253; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])54; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 155; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 429496729556; CHECK-NEXT: br i1 false, label [[LOOP]], label [[EXIT:%.*]]57; CHECK: exit:58; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[LSR_IV_NEXT]], 1259; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i64 [[TMP0]], 1260; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 429496722161; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], [[IV_NEXT]]62; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[TMP3]] to i3263; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i32 [[TMP]], 3264; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP3]], i64 0, i64 [[IV_NEXT]]65; CHECK-NEXT: ret i64 [[SPEC_SELECT]]66;67entry:68 br label %loop69 70loop:71 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]72 %iv1 = phi i32 [ -74, %entry ], [ %iv1.next, %loop ]73 %iv2 = phi i32 [ 83, %entry ], [ %iv2.next, %loop ]74 %iv3 = phi i32 [ 0, %entry ], [ %iv3.next, %loop ]75 call void @use.i32(i32 %iv3)76 %iv.next = add nuw nsw i64 %iv, 177 %iv1.next = add nuw nsw i32 %iv1, 178 %iv2.next = add nsw i32 %iv2, -179 %iv3.next = add nuw nsw i32 %iv3, 180 br i1 false, label %loop, label %exit81 82exit:83 %i2 = udiv i32 %iv2.next, 1284 %i5 = mul nuw nsw i32 %i2, 1285 %i6 = add i32 %iv1, %i586 %cmp3 = icmp ult i32 %i6, 3287 %spec.select = select i1 %cmp3, i64 0, i64 %iv.next88 ret i64 %spec.select89}90 91define i32 @test_pr62852() {92; CHECK-LABEL: define i32 @test_pr62852() {93; CHECK-NEXT: entry:94; CHECK-NEXT: br label [[LOOP:%.*]]95; CHECK: loop:96; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[LOOP]] ], [ -1, [[ENTRY:%.*]] ]97; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 2, [[ENTRY]] ]98; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ [[DEC_1:%.*]], [[LOOP]] ]99; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV1]], 1100; CHECK-NEXT: [[DEC_1]] = add nsw i32 [[IV_1]], -1101; CHECK-NEXT: call void @use(i64 [[TMP0]])102; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1103; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i32104; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i64 [[LSR_IV1]], 1105; CHECK-NEXT: [[CMP6_1:%.*]] = icmp sgt i32 [[TMP]], 0106; CHECK-NEXT: br i1 [[CMP6_1]], label [[LOOP]], label [[EXIT:%.*]]107; CHECK: exit:108; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT]])109; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT2]])110; CHECK-NEXT: [[TMP3:%.*]] = urem i32 [[DEC_1]], 53111; CHECK-NEXT: ret i32 [[TMP3]]112;113entry:114 br label %loop115 116loop:117 %iv.1 = phi i32 [ 1, %entry ], [ %dec.1, %loop ]118 %iv.2 = phi i64 [ 0, %entry ], [ %inc.1, %loop ]119 %inc.1 = add nsw i64 %iv.2, 1120 %dec.1 = add nsw i32 %iv.1, -1121 call void @use(i64 %iv.2)122 %cmp6.1 = icmp sgt i32 %iv.1, 0123 br i1 %cmp6.1, label %loop, label %exit124 125exit:126 %iv.1.ext = zext i32 %iv.1 to i64127 call void @use(i64 %iv.1.ext)128 call void @use(i64 %iv.2)129 %rem = urem i32 %dec.1, 53130 ret i32 %rem131}132 133define i64 @test_normalization_failure_in_any_extend(ptr %i, i64 %i1, i8 %i25) {134; CHECK-LABEL: define i64 @test_normalization_failure_in_any_extend135; CHECK-SAME: (ptr [[I:%.*]], i64 [[I1:%.*]], i8 [[I25:%.*]]) {136; CHECK-NEXT: entry:137; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]138; CHECK: loop.1.header:139; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_1_LATCH:%.*]] ]140; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[I1]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP_1_LATCH]] ]141; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[IV_2]], 2142; CHECK-NEXT: br label [[LOOP_2:%.*]]143; CHECK: loop.2:144; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP_2]] ], [ 2, [[LOOP_1_HEADER]] ]145; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1146; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 [[LSR_IV_NEXT]], 0147; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_2]], label [[LOOP_3_PREHEADER:%.*]]148; CHECK: loop.3.preheader:149; CHECK-NEXT: br label [[LOOP_3:%.*]]150; CHECK: loop.3:151; CHECK-NEXT: [[LSR_IV5:%.*]] = phi i64 [ 0, [[LOOP_3_PREHEADER]] ], [ [[LSR_IV_NEXT6:%.*]], [[LOOP_3]] ]152; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ 2, [[LOOP_3_PREHEADER]] ], [ [[LSR_IV_NEXT2:%.*]], [[LOOP_3]] ]153; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[IV_5_NEXT:%.*]], [[LOOP_3]] ], [ 1, [[LOOP_3_PREHEADER]] ]154; CHECK-NEXT: [[IV_5_NEXT]] = add nsw i32 [[IV_5]], -1155; CHECK-NEXT: [[LSR:%.*]] = trunc i32 [[IV_5_NEXT]] to i8156; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i64 [[LSR_IV1]], -1157; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[LSR_IV_NEXT2]] to i32158; CHECK-NEXT: [[LSR_IV_NEXT6]] = add nsw i64 [[LSR_IV5]], -1159; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[TMP]], 0160; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_3]], label [[LOOP_1_LATCH]]161; CHECK: loop.1.latch:162; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i32 [[IV_1]], 1163; CHECK-NEXT: [[TMP1]] = sub i64 [[TMP0]], [[LSR_IV_NEXT6]]164; CHECK-NEXT: [[C_3:%.*]] = icmp eq i32 [[IV_1_NEXT]], 8165; CHECK-NEXT: br i1 [[C_3]], label [[EXIT:%.*]], label [[LOOP_1_HEADER]]166; CHECK: exit:167; CHECK-NEXT: call void @use.i32(i32 [[IV_5_NEXT]])168; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[IV_2]], 1169; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[LSR_IV_NEXT6]]170; CHECK-NEXT: call void @use(i64 [[TMP3]])171; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT2]])172; CHECK-NEXT: [[TMP4:%.*]] = udiv i32 [[IV_5_NEXT]], 53173; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8174; CHECK-NEXT: [[TMP6:%.*]] = mul i8 [[TMP5]], 53175; CHECK-NEXT: [[TMP7:%.*]] = sub i8 [[LSR]], [[TMP6]]176; CHECK-NEXT: call void @use.i8(i8 [[TMP7]])177; CHECK-NEXT: [[I26:%.*]] = xor i8 [[I25]], 5178; CHECK-NEXT: [[I27:%.*]] = zext i8 [[I26]] to i64179; CHECK-NEXT: ret i64 [[I27]]180;181entry:182 br label %loop.1.header183 184loop.1.header:185 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ]186 %iv.2 = phi i64 [ %i1, %entry ], [ %iv.6.next, %loop.1.latch ]187 br label %loop.2188 189loop.2:190 %iv.3 = phi i32 [ 1, %loop.1.header ], [ %iv.3.next, %loop.2 ]191 %iv.4 = phi i64 [ %iv.2, %loop.1.header ], [ %iv.4.next, %loop.2 ]192 %iv.4.next = add nsw i64 %iv.4, 1193 %iv.3.next = add nsw i32 %iv.3, -1194 %c.1 = icmp sgt i32 %iv.3, 0195 br i1 %c.1, label %loop.2, label %loop.3196 197loop.3:198 %iv.5 = phi i32 [ 1, %loop.2 ], [ %iv.5.next, %loop.3 ]199 %iv.6 = phi i64 [ %iv.4.next, %loop.2 ], [ %iv.6.next, %loop.3 ]200 %iv.6.next = add nsw i64 %iv.6, 1201 %iv.5.next = add nsw i32 %iv.5, -1202 %c.2 = icmp sgt i32 %iv.5, 0203 br i1 %c.2, label %loop.3, label %loop.1.latch204 205loop.1.latch:206 %iv.1.next = add nuw nsw i32 %iv.1, 1207 %c.3 = icmp eq i32 %iv.1.next, 8208 br i1 %c.3, label %exit, label %loop.1.header209 210exit:211 call void @use.i32(i32 %iv.5.next)212 %i21 = zext i32 %iv.5 to i64213 call void @use(i64 %iv.6)214 call void @use(i64 %i21)215 %i22 = urem i32 %iv.5.next, 53216 %i23 = trunc i32 %i22 to i8217 call void @use.i8(i8 %i23)218 %i26 = xor i8 %i25, 5219 %i27 = zext i8 %i26 to i64220 ret i64 %i27221}222