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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -loop-reduce -verify-scev -S %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-apple-macos"6 7define i64 @test_pr62660() {8; CHECK-LABEL: define i64 @test_pr62660() {9; CHECK-NEXT: entry:10; CHECK-NEXT: br label [[LOOP:%.*]]11; CHECK: loop:12; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ -1, [[ENTRY:%.*]] ]13; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]14; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV]], 115; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[TMP0]] to i3216; CHECK-NEXT: [[CONV1:%.*]] = and i32 [[TMP]], 6553517; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[IV]], -118; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], [[CONV1]]19; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 120; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 121; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 822; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]23; CHECK: exit:24; CHECK-NEXT: ret i64 [[LSR_IV_NEXT]]25;26entry:27 br label %loop28 29loop:30 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]31 %conv1 = and i32 %iv, 6553532 %add = add nsw i32 %iv, -133 %sub = add i32 %add, %conv134 %cmp = icmp sgt i32 %sub, 835 %iv.next = add nuw nsw i32 %iv, 136 br i1 %cmp, label %loop, label %exit37 38exit:39 %conv5 = zext i32 %iv to i6440 ret i64 %conv541}42 43 44define void @pr63840_crash(i64 %sext974, i64 %sext982, i8 %x) {45; CHECK-LABEL: define void @pr63840_crash46; CHECK-SAME: (i64 [[SEXT974:%.*]], i64 [[SEXT982:%.*]], i8 [[X:%.*]]) {47; CHECK-NEXT: bb:48; CHECK-NEXT: [[TMP0:%.*]] = sext i8 [[X]] to i6449; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[TMP0]], 150; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[SEXT982]], [[SEXT974]]51; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], [[TMP2]]52; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[TMP0]], [[SEXT974]]53; CHECK-NEXT: br label [[BB983:%.*]]54; CHECK: bb983:55; CHECK-NEXT: [[LSR_IV7:%.*]] = phi i64 [ [[LSR_IV_NEXT8:%.*]], [[BB983]] ], [ [[TMP4]], [[BB:%.*]] ]56; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[BB983]] ], [ [[TMP3]], [[BB]] ]57; CHECK-NEXT: [[LSR_IV_NEXT2]] = sub i64 [[LSR_IV1]], [[SEXT982]]58; CHECK-NEXT: [[LSR_IV_NEXT8]] = sub i64 [[LSR_IV7]], [[SEXT982]]59; CHECK-NEXT: br i1 false, label [[BB992:%.*]], label [[BB983]]60; CHECK: bb992:61; CHECK-NEXT: [[LSR_IV_NEXT8_LCSSA:%.*]] = phi i64 [ [[LSR_IV_NEXT8]], [[BB983]] ]62; CHECK-NEXT: [[SEXT1046:%.*]] = sext i8 [[X]] to i6463; CHECK-NEXT: br label [[BB1092:%.*]]64; CHECK: bb1051:65; CHECK-NEXT: ret void66; CHECK: bb1053:67; CHECK-NEXT: [[ADD1054:%.*]] = add i64 [[PHI1094:%.*]], [[SEXT1046]]68; CHECK-NEXT: br i1 false, label [[BB1059:%.*]], label [[BB1064SPLIT:%.*]]69; CHECK: bb1059:70; CHECK-NEXT: [[ADD1061:%.*]] = add i64 [[ADD1054]], [[SEXT1046]]71; CHECK-NEXT: store i64 [[ADD1061]], ptr addrspace(1) null, align 872; CHECK-NEXT: br i1 false, label [[BB1059_BB1064_CRIT_EDGE:%.*]], label [[BB1092]]73; CHECK: bb1064split:74; CHECK-NEXT: br label [[BB1064:%.*]]75; CHECK: bb1059.bb1064_crit_edge:76; CHECK-NEXT: [[LSR_IV_NEXT4_LCSSA6:%.*]] = phi i64 [ [[LSR_IV_NEXT4:%.*]], [[BB1059]] ]77; CHECK-NEXT: br label [[BB1064]]78; CHECK: bb1064:79; CHECK-NEXT: [[PHI1065:%.*]] = phi i64 [ [[LSR_IV_NEXT4_LCSSA6]], [[BB1059_BB1064_CRIT_EDGE]] ], [ 0, [[BB1064SPLIT]] ]80; CHECK-NEXT: ret void81; CHECK: bb1092:82; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i64 [ [[LSR_IV_NEXT4]], [[BB1059]] ], [ [[LSR_IV1]], [[BB992]] ]83; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB1059]] ], [ -1, [[BB992]] ]84; CHECK-NEXT: [[PHI1094]] = phi i64 [ [[LSR_IV_NEXT8_LCSSA]], [[BB992]] ], [ [[ADD1054]], [[BB1059]] ]85; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 186; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i64 [[LSR_IV3]], [[SEXT1046]]87; CHECK-NEXT: [[ICMP1050:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 088; CHECK-NEXT: br i1 [[ICMP1050]], label [[BB1053:%.*]], label [[BB1051:%.*]]89;90bb:91 %sub975 = sub i64 0, %sext97492 br label %bb98393 94bb983: ; preds = %bb983, %bb95 %phi985 = phi i64 [ %sub989, %bb983 ], [ %sub975, %bb ]96 %sub989 = sub i64 %phi985, %sext98297 br i1 false, label %bb992, label %bb98398 99bb992: ; preds = %bb983100 %sext1046 = sext i8 %x to i64101 %add1047 = add i64 %sub989, %sext1046102 br label %bb1092103 104bb1051: ; preds = %bb1092105 ret void106 107bb1053: ; preds = %bb1092108 %add1054 = add i64 %phi1094, %sext1046109 br i1 false, label %bb1059, label %bb1064110 111bb1059: ; preds = %bb1053112 %add1060 = add i64 %phi1093, 1113 %add1061 = add i64 %add1054, %sext1046114 store i64 %add1061, ptr addrspace(1) null, align 8115 br i1 false, label %bb1064, label %bb1092116 117bb1064: ; preds = %bb1059, %bb1053118 %phi1065 = phi i64 [ 0, %bb1053 ], [ %add1061, %bb1059 ]119 ret void120 121bb1092: ; preds = %bb1059, %bb992122 %phi1093 = phi i64 [ 0, %bb992 ], [ %add1060, %bb1059 ]123 %phi1094 = phi i64 [ %add1047, %bb992 ], [ %add1054, %bb1059 ]124 %icmp1050 = icmp ult i64 %phi1093, 0125 br i1 %icmp1050, label %bb1053, label %bb1051126}127