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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -loop-reduce -S %s | FileCheck %s3; PR180004 5target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128"6target triple = "x86_64-unknown-linux-gnu"7 8@a = global i32 0, align 49@b = common global i32 0, align 410@e = common global i8 0, align 111@d = common global i32 0, align 412@c = common global i32 0, align 413@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 114 15define i32 @foo() {16; CHECK-LABEL: define i32 @foo() {17; CHECK-NEXT: [[ENTRY:.*:]]18; CHECK-NEXT: [[DOTPR:%.*]] = load i32, ptr @b, align 419; CHECK-NEXT: [[CMP10:%.*]] = icmp slt i32 [[DOTPR]], 120; CHECK-NEXT: br i1 [[CMP10]], label %[[OUTER_PH:.*]], label %[[ENTRY_ELSE:.*]]21; CHECK: [[ENTRY_ELSE]]:22; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr @c, align 423; CHECK-NEXT: br label %[[MERGE:.*]]24; CHECK: [[OUTER_PH]]:25; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 426; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 027; CHECK-NEXT: br i1 [[TOBOOL]], label %[[OUTER_HEADER_PREHEADER:.*]], label %[[P_ELSE:.*]]28; CHECK: [[OUTER_HEADER_PREHEADER]]:29; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]30; CHECK: [[OUTER_HEADER]]:31; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[INC:%.*]], %[[OUTER_LATCH:.*]] ], [ [[DOTPR]], %[[OUTER_HEADER_PREHEADER]] ]32; CHECK-NEXT: br label %[[INNER_LOOP:.*]]33; CHECK: [[INNER_LOOP]]:34; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[INNER_LOOP]] ], [ 516, %[[OUTER_HEADER]] ]35; CHECK-NEXT: [[TMP2:%.*]] = phi i8 [ 1, %[[OUTER_HEADER]] ], [ [[DEC:%.*]], %[[INNER_LOOP]] ]36; CHECK-NEXT: [[SHL:%.*]] = add i32 [[LSR_IV]], -25837; CHECK-NEXT: store i32 [[SHL]], ptr @c, align 438; CHECK-NEXT: [[DEC]] = add i8 [[TMP2]], -139; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -25840; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i8 [[DEC]], -141; CHECK-NEXT: br i1 [[CMP2]], label %[[INNER_LOOP]], label %[[OUTER_LATCH]]42; CHECK: [[OUTER_LATCH]]:43; CHECK-NEXT: [[LSR_IV_NEXT_LCSSA:%.*]] = phi i32 [ [[LSR_IV_NEXT]], %[[INNER_LOOP]] ]44; CHECK-NEXT: store i32 0, ptr @d, align 445; CHECK-NEXT: [[INC]] = add nsw i32 [[TMP1]], 146; CHECK-NEXT: store i32 [[INC]], ptr @b, align 447; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 048; CHECK-NEXT: br i1 [[CMP]], label %[[OUTER_HEADER]], label %[[OUTER_EXIT:.*]]49; CHECK: [[OUTER_EXIT]]:50; CHECK-NEXT: [[LSR_IV_NEXT_LCSSA_LCSSA:%.*]] = phi i32 [ [[LSR_IV_NEXT_LCSSA]], %[[OUTER_LATCH]] ]51; CHECK-NEXT: store i8 [[DEC]], ptr @e, align 152; CHECK-NEXT: br label %[[MERGE]]53; CHECK: [[MERGE]]:54; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[DOTPRE]], %[[ENTRY_ELSE]] ], [ [[LSR_IV_NEXT_LCSSA_LCSSA]], %[[OUTER_EXIT]] ]55; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @bar(i32 [[TMP3]])56; CHECK-NEXT: br label %[[RETURN:.*]]57; CHECK: [[P_ELSE]]:58; CHECK-NEXT: store i8 1, ptr @e, align 159; CHECK-NEXT: store i32 0, ptr @d, align 460; CHECK-NEXT: br label %[[RETURN]]61; CHECK: [[RETURN]]:62; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, %[[MERGE]] ], [ 1, %[[P_ELSE]] ]63; CHECK-NEXT: ret i32 [[RETVAL_0]]64;65entry:66 %.pr = load i32, ptr @b, align 467 %cmp10 = icmp slt i32 %.pr, 168 br i1 %cmp10, label %outer.ph, label %entry.else69 70entry.else:71 %.pre = load i32, ptr @c, align 472 br label %merge73 74outer.ph:75 %0 = load i32, ptr @a, align 476 %tobool = icmp eq i32 %0, 077 br i1 %tobool, label %outer.header, label %p.else78 79outer.header:80 %1 = phi i32 [ %.pr, %outer.ph ], [ %inc, %outer.latch ]81 br label %inner.loop82 83inner.loop:84 %iv = phi i32 [ 1, %outer.header ], [ %iv.next, %inner.loop ]85 %2 = phi i8 [ 1, %outer.header ], [ %dec, %inner.loop ]86 %conv7 = mul i32 %iv, 25887 %shl = and i32 %conv7, 51088 store i32 %shl, ptr @c, align 489 %dec = add i8 %2, -190 %cmp2 = icmp sgt i8 %dec, -191 %iv.next = add i32 %iv, -192 br i1 %cmp2, label %inner.loop, label %outer.latch93 94outer.latch:95 store i32 0, ptr @d, align 496 %inc = add nsw i32 %1, 197 store i32 %inc, ptr @b, align 498 %cmp = icmp slt i32 %1, 099 br i1 %cmp, label %outer.header, label %outer.exit100 101outer.exit:102 store i8 %dec, ptr @e, align 1103 br label %merge104 105merge:106 %3 = phi i32 [ %.pre, %entry.else ], [ %shl, %outer.exit ]107 %call = tail call i32 @bar(i32 %3)108 br label %return109 110p.else:111 store i8 1, ptr @e, align 1112 store i32 0, ptr @d, align 4113 br label %return114 115return:116 %retval.0 = phi i32 [ 0, %merge ], [ 1, %p.else ]117 ret i32 %retval.0118}119 120declare i32 @bar(i32)121 122