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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt < %s -loop-reduce -S | FileCheck %s3 4; This test tests several things. The load and store should use the5; same address instead of having it computed twice, and SCEVExpander should6; be able to reconstruct the full getelementptr, despite it having a few7; obstacles set in its way.8; We only check that the inner loop (bb1-bb2) is "reduced" because LSR9; currently only operates on inner loops.10 11target datalayout = "e-p:64:64:64-p1:16:16:16-n16:32:64"12 13define void @foo(i64 %n, i64 %m, i64 %o, i64 %q, ptr addrspace(1) nocapture %p) nounwind {14; CHECK-LABEL: define void @foo(15; CHECK-SAME: i64 [[N:%.*]], i64 [[M:%.*]], i64 [[O:%.*]], i64 [[Q:%.*]], ptr addrspace(1) captures(none) [[P:%.*]]) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: entry:17; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i64 [[N]], 018; CHECK-NEXT: br i1 [[TMP]], label [[BB_NPH3:%.*]], label [[RETURN:%.*]]19; CHECK: bb.nph:20; CHECK-NEXT: br label [[BB1:%.*]]21; CHECK: bb1:22; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr addrspace(1) [ [[SCEVGEP3:%.*]], [[BB2:%.*]] ], [ [[LSR_IV:%.*]], [[BB_NPH:%.*]] ]23; CHECK-NEXT: [[J_01:%.*]] = phi i64 [ [[TMP9:%.*]], [[BB2]] ], [ 0, [[BB_NPH]] ]24; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr addrspace(1) [[LSR_IV2]], align 825; CHECK-NEXT: [[TMP7:%.*]] = fdiv double [[TMP6]], 2.100000e+0026; CHECK-NEXT: store double [[TMP7]], ptr addrspace(1) [[LSR_IV2]], align 827; CHECK-NEXT: [[TMP9]] = add i64 [[J_01]], 128; CHECK-NEXT: br label [[BB2]]29; CHECK: bb2:30; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i8, ptr addrspace(1) [[LSR_IV2]], i16 831; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[M]]32; CHECK-NEXT: br i1 [[TMP10]], label [[BB1]], label [[BB2_BB3_CRIT_EDGE:%.*]]33; CHECK: bb2.bb3_crit_edge:34; CHECK-NEXT: br label [[BB3:%.*]]35; CHECK: bb3:36; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[I_02:%.*]], 137; CHECK-NEXT: br label [[BB4:%.*]]38; CHECK: bb4:39; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[LSR_IV]], i16 [[TMP4:%.*]]40; CHECK-NEXT: [[TMP12:%.*]] = icmp slt i64 [[TMP11]], [[N]]41; CHECK-NEXT: br i1 [[TMP12]], label [[BB2_PREHEADER:%.*]], label [[BB4_RETURN_CRIT_EDGE:%.*]]42; CHECK: bb4.return_crit_edge:43; CHECK-NEXT: br label [[BB4_RETURN_CRIT_EDGE_SPLIT:%.*]]44; CHECK: bb4.return_crit_edge.split:45; CHECK-NEXT: br label [[RETURN]]46; CHECK: bb.nph3:47; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i64 [[M]], 048; CHECK-NEXT: br i1 [[TMP13]], label [[BB_NPH3_SPLIT:%.*]], label [[BB4_RETURN_CRIT_EDGE_SPLIT]]49; CHECK: bb.nph3.split:50; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[P]], i16 -2391251; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[Q]], [[O]]52; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], [[N]]53; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 3754; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i1655; CHECK-NEXT: [[TMP4]] = shl i16 [[TMP3]], 356; CHECK-NEXT: br label [[BB2_PREHEADER]]57; CHECK: bb2.preheader:58; CHECK-NEXT: [[LSR_IV]] = phi ptr addrspace(1) [ [[SCEVGEP]], [[BB_NPH3_SPLIT]] ], [ [[SCEVGEP1]], [[BB4]] ]59; CHECK-NEXT: [[I_02]] = phi i64 [ [[TMP11]], [[BB4]] ], [ 0, [[BB_NPH3_SPLIT]] ]60; CHECK-NEXT: br i1 true, label [[BB_NPH]], label [[BB3]]61; CHECK: return:62; CHECK-NEXT: ret void63;64entry:65 %tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1]66 br i1 %tmp, label %bb.nph3, label %return67 68bb.nph: ; preds = %bb2.preheader69 %tmp1 = mul i64 %tmp16, %i.02 ; <i64> [#uses=1]70 %tmp2 = mul i64 %tmp19, %i.02 ; <i64> [#uses=1]71 br label %bb172 73bb1: ; preds = %bb2, %bb.nph74 %j.01 = phi i64 [ %tmp9, %bb2 ], [ 0, %bb.nph ] ; <i64> [#uses=3]75 %tmp3 = add i64 %j.01, %tmp1 ; <i64> [#uses=1]76 %tmp4 = add i64 %j.01, %tmp2 ; <i64> [#uses=1]77 %z0 = add i64 %tmp3, 520378 %tmp5 = getelementptr double, ptr addrspace(1) %p, i64 %z0 ; <ptr addrspace(1)> [#uses=1]79 %tmp6 = load double, ptr addrspace(1) %tmp5, align 8 ; <double> [#uses=1]80 %tmp7 = fdiv double %tmp6, 2.100000e+00 ; <double> [#uses=1]81 %z1 = add i64 %tmp4, 520382 %tmp8 = getelementptr double, ptr addrspace(1) %p, i64 %z1 ; <ptr addrspace(1)> [#uses=1]83 store double %tmp7, ptr addrspace(1) %tmp8, align 884 %tmp9 = add i64 %j.01, 1 ; <i64> [#uses=2]85 br label %bb286 87bb2: ; preds = %bb188 %tmp10 = icmp slt i64 %tmp9, %m ; <i1> [#uses=1]89 br i1 %tmp10, label %bb1, label %bb2.bb3_crit_edge90 91bb2.bb3_crit_edge: ; preds = %bb292 br label %bb393 94bb3: ; preds = %bb2.preheader, %bb2.bb3_crit_edge95 %tmp11 = add i64 %i.02, 1 ; <i64> [#uses=2]96 br label %bb497 98bb4: ; preds = %bb399 %tmp12 = icmp slt i64 %tmp11, %n ; <i1> [#uses=1]100 br i1 %tmp12, label %bb2.preheader, label %bb4.return_crit_edge101 102bb4.return_crit_edge: ; preds = %bb4103 br label %bb4.return_crit_edge.split104 105bb4.return_crit_edge.split: ; preds = %bb.nph3, %bb4.return_crit_edge106 br label %return107 108bb.nph3: ; preds = %entry109 %tmp13 = icmp sgt i64 %m, 0 ; <i1> [#uses=1]110 %tmp14 = mul i64 %n, 37 ; <i64> [#uses=1]111 %tmp15 = mul i64 %tmp14, %o ; <i64> [#uses=1]112 %tmp16 = mul i64 %tmp15, %q ; <i64> [#uses=1]113 %tmp17 = mul i64 %n, 37 ; <i64> [#uses=1]114 %tmp18 = mul i64 %tmp17, %o ; <i64> [#uses=1]115 %tmp19 = mul i64 %tmp18, %q ; <i64> [#uses=1]116 br i1 %tmp13, label %bb.nph3.split, label %bb4.return_crit_edge.split117 118bb.nph3.split: ; preds = %bb.nph3119 br label %bb2.preheader120 121bb2.preheader: ; preds = %bb.nph3.split, %bb4122 %i.02 = phi i64 [ %tmp11, %bb4 ], [ 0, %bb.nph3.split ] ; <i64> [#uses=3]123 br i1 true, label %bb.nph, label %bb3124 125return: ; preds = %bb4.return_crit_edge.split, %entry126 ret void127}128