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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -loop-reduce < %s | FileCheck %s3 4; Address Space 10 is non-integral. The optimizer is not allowed to use5; ptrtoint/inttoptr instructions. Make sure that this doesn't happen6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12"7target triple = "x86_64-unknown-linux-gnu"8 9; How exactly SCEV chooses to materialize isn't all that important, as10; long as it doesn't try to round-trip through integers. As of this writing,11; it emits a byte-wise gep, which is fine.12define void @japi1__unsafe_getindex_65028(ptr addrspace(10) %arg) {13; CHECK-LABEL: define void @japi1__unsafe_getindex_6502814; CHECK-SAME: (ptr addrspace(10) [[ARG:%.*]]) {15; CHECK-NEXT: top:16; CHECK-NEXT: br label [[L86:%.*]]17; CHECK: L86:18; CHECK-NEXT: [[LSR_IV4:%.*]] = phi i64 [ [[LSR_IV_NEXT5:%.*]], [[L86]] ], [ -2, [[TOP:%.*]] ]19; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nsw i64 [[LSR_IV4]], 220; CHECK-NEXT: br i1 false, label [[L86]], label [[IF29:%.*]]21; CHECK: if29:22; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(10) [[ARG]], i64 -823; CHECK-NEXT: br label [[IF31:%.*]]24; CHECK: if31:25; CHECK-NEXT: %"#temp#1.sroa.0.022" = phi i64 [ 0, [[IF29]] ], [ [[TMP3_LCSSA:%.*]], [[IF38:%.*]] ]26; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV_NEXT5]], %"#temp#1.sroa.0.022"27; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 328; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(10) [[SCEVGEP]], i64 [[TMP1]]29; CHECK-NEXT: br label [[L119:%.*]]30; CHECK: L119:31; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr addrspace(10) [ [[SCEVGEP3:%.*]], [[L119]] ], [ [[SCEVGEP1]], [[IF31]] ]32; CHECK-NEXT: [[I5_0:%.*]] = phi i64 [ %"#temp#1.sroa.0.022", [[IF31]] ], [ [[TMP3:%.*]], [[L119]] ]33; CHECK-NEXT: [[TMP3]] = add i64 [[I5_0]], 134; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i8, ptr addrspace(10) [[LSR_IV2]], i64 835; CHECK-NEXT: br i1 false, label [[L119]], label [[IF38]]36; CHECK: if38:37; CHECK-NEXT: [[TMP3_LCSSA]] = phi i64 [ [[TMP3]], [[L119]] ]38; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(10) [[SCEVGEP3]], align 839; CHECK-NEXT: br i1 true, label [[DONE:%.*]], label [[IF31]]40; CHECK: done:41; CHECK-NEXT: ret void42;43top:44 br label %L8645 46L86: ; preds = %L86, %top47 %i.0 = phi i64 [ 0, %top ], [ %tmp, %L86 ]48 %tmp = add i64 %i.0, 149 br i1 false, label %L86, label %if2950 51if29: ; preds = %L8652 %tmp1 = shl i64 %tmp, 153 %tmp2 = add i64 %tmp1, -254 br label %if3155 56if31: ; preds = %if38, %if2957 %"#temp#1.sroa.0.022" = phi i64 [ 0, %if29 ], [ %tmp3, %if38 ]58 br label %L11959 60L119: ; preds = %L119, %if3161 %i5.0 = phi i64 [ %"#temp#1.sroa.0.022", %if31 ], [ %tmp3, %L119 ]62 %tmp3 = add i64 %i5.0, 163 br i1 false, label %L119, label %if3864 65if38: ; preds = %L11966 %tmp4 = add i64 %tmp2, %i5.067 %tmp5 = getelementptr i64, ptr addrspace(10) %arg, i64 %tmp468 %tmp6 = load i64, ptr addrspace(10) %tmp569 br i1 true, label %done, label %if3170 71done: ; preds = %if3872 ret void73}74