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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -loop-reduce -S | FileCheck %s3; REQUIRES: x86-registered-target4 5target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"6target triple = "x86_64-unknown-linux-gnu"7 8; FIXME: iv.next is supposed to be inserted in the backedge.9define i32 @test_01(ptr %p, i64 %len, i32 %x) {10; CHECK-LABEL: @test_01(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 -413; CHECK-NEXT: br label [[LOOP:%.*]]14; CHECK: loop:15; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]16; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 017; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]18; CHECK: backedge:19; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 220; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP0]]21; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[SCEVGEP1]] unordered, align 422; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]23; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -124; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]25; CHECK: exit:26; CHECK-NEXT: ret i32 -127; CHECK: failure:28; CHECK-NEXT: unreachable29;30entry:31 br label %loop32 33loop: ; preds = %backedge, %entry34 %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]35 %iv.next = add nsw i64 %iv, -136 %cond_1 = icmp eq i64 %iv, 037 br i1 %cond_1, label %exit, label %backedge38 39backedge: ; preds = %loop40 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next41 %loaded = load atomic i32, ptr %addr unordered, align 442 %cond_2 = icmp eq i32 %loaded, %x43 br i1 %cond_2, label %failure, label %loop44 45exit: ; preds = %loop46 ret i32 -147 48failure: ; preds = %backedge49 unreachable50}51 52define i32 @test_02(ptr %p, i64 %len, i32 %x) {53; CHECK-LABEL: @test_02(54; CHECK-NEXT: entry:55; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 -456; CHECK-NEXT: br label [[LOOP:%.*]]57; CHECK: loop:58; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]59; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 060; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]61; CHECK: backedge:62; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[LSR_IV]], 263; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP0]]64; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[SCEVGEP1]] unordered, align 465; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]66; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -167; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]68; CHECK: exit:69; CHECK-NEXT: ret i32 -170; CHECK: failure:71; CHECK-NEXT: unreachable72;73entry:74 %start = add i64 %len, -175 br label %loop76 77loop: ; preds = %backedge, %entry78 %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]79 %iv.next = add nsw i64 %iv, -180 %iv.offset = add i64 %iv, 181 %iv.next.offset = add i64 %iv.next, 182 %cond_1 = icmp eq i64 %iv.offset, 083 br i1 %cond_1, label %exit, label %backedge84 85backedge: ; preds = %loop86 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next.offset87 %loaded = load atomic i32, ptr %addr unordered, align 488 %cond_2 = icmp eq i32 %loaded, %x89 br i1 %cond_2, label %failure, label %loop90 91exit: ; preds = %loop92 ret i32 -193 94failure: ; preds = %backedge95 unreachable96}97 98define i32 @test_03(ptr %p, i64 %len, i32 %x) {99; CHECK-LABEL: @test_03(100; CHECK-NEXT: entry:101; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 -4102; CHECK-NEXT: br label [[LOOP:%.*]]103; CHECK: loop:104; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]105; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 0106; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]107; CHECK: backedge:108; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[LSR_IV]], 2109; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP0]]110; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[SCEVGEP1]] unordered, align 4111; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]112; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1113; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]114; CHECK: exit:115; CHECK-NEXT: ret i32 -1116; CHECK: failure:117; CHECK-NEXT: unreachable118;119entry:120 %start = add i64 %len, -100121 br label %loop122 123loop: ; preds = %backedge, %entry124 %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]125 %iv.next = add nsw i64 %iv, -1126 %iv.offset = add i64 %iv, 100127 %iv.next.offset = add i64 %iv.next, 100128 %cond_1 = icmp eq i64 %iv.offset, 0129 br i1 %cond_1, label %exit, label %backedge130 131backedge: ; preds = %loop132 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next.offset133 %loaded = load atomic i32, ptr %addr unordered, align 4134 %cond_2 = icmp eq i32 %loaded, %x135 br i1 %cond_2, label %failure, label %loop136 137exit: ; preds = %loop138 ret i32 -1139 140failure: ; preds = %backedge141 unreachable142}143 144define i32 @test_04(ptr %p, i64 %len, i32 %x) {145; CHECK-LABEL: @test_04(146; CHECK-NEXT: entry:147; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 -4148; CHECK-NEXT: br label [[LOOP:%.*]]149; CHECK: loop:150; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]151; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0152; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]153; CHECK: backedge:154; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2155; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP0]]156; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[SCEVGEP1]] unordered, align 4157; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]158; CHECK-NEXT: [[IV_NEXT]] = sub i64 [[IV]], 1159; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]160; CHECK: exit:161; CHECK-NEXT: ret i32 -1162; CHECK: failure:163; CHECK-NEXT: unreachable164;165entry:166 br label %loop167 168loop: ; preds = %backedge, %entry169 %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]170 %iv.next = sub i64 %iv, 1171 %cond_1 = icmp eq i64 %iv, 0172 br i1 %cond_1, label %exit, label %backedge173 174backedge: ; preds = %loop175 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next176 %loaded = load atomic i32, ptr %addr unordered, align 4177 %cond_2 = icmp eq i32 %loaded, %x178 br i1 %cond_2, label %failure, label %loop179 180exit: ; preds = %loop181 ret i32 -1182 183failure: ; preds = %backedge184 unreachable185}186 187define i32 @test_05(ptr %p, i64 %len, i32 %x) {188; CHECK-LABEL: @test_05(189; CHECK-NEXT: entry:190; CHECK-NEXT: br label [[LOOP:%.*]]191; CHECK: loop:192; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]193; CHECK-NEXT: [[IV_NEXT]] = mul i64 [[IV]], 2194; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0195; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]196; CHECK: backedge:197; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[IV_NEXT]]198; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[ADDR]] unordered, align 4199; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]200; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]201; CHECK: exit:202; CHECK-NEXT: ret i32 -1203; CHECK: failure:204; CHECK-NEXT: unreachable205;206entry:207 br label %loop208 209loop: ; preds = %backedge, %entry210 %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]211 %iv.next = mul i64 %iv, 2212 %cond_1 = icmp eq i64 %iv, 0213 br i1 %cond_1, label %exit, label %backedge214 215backedge: ; preds = %loop216 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next217 %loaded = load atomic i32, ptr %addr unordered, align 4218 %cond_2 = icmp eq i32 %loaded, %x219 br i1 %cond_2, label %failure, label %loop220 221exit: ; preds = %loop222 ret i32 -1223 224failure: ; preds = %backedge225 unreachable226}227 228define i32 @test_06(ptr %p, i64 %len, i32 %x, i64 %step) {229; CHECK-LABEL: @test_06(230; CHECK-NEXT: entry:231; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[STEP:%.*]], 2232; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[TMP0]]233; CHECK-NEXT: br label [[LOOP:%.*]]234; CHECK: loop:235; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]236; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[STEP]]237; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[STEP]], [[IV_NEXT]]238; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]239; CHECK: backedge:240; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[IV]], 2241; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP1]]242; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, ptr [[SCEVGEP1]] unordered, align 4243; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]244; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]245; CHECK: exit:246; CHECK-NEXT: ret i32 -1247; CHECK: failure:248; CHECK-NEXT: unreachable249;250entry:251 br label %loop252 253loop: ; preds = %backedge, %entry254 %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]255 %iv.next = add nsw i64 %iv, %step256 %cond_1 = icmp eq i64 %iv, 0257 br i1 %cond_1, label %exit, label %backedge258 259backedge: ; preds = %loop260 %addr = getelementptr inbounds i32, ptr %p, i64 %iv.next261 %loaded = load atomic i32, ptr %addr unordered, align 4262 %cond_2 = icmp eq i32 %loaded, %x263 br i1 %cond_2, label %failure, label %loop264 265exit: ; preds = %loop266 ret i32 -1267 268failure: ; preds = %backedge269 unreachable270}271