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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt < %s -loop-reduce -S | FileCheck %s3 4; LSR shouldn't consider %t8 to be an interesting user of %t6, and it5; should be able to form pretty GEPs.6 7target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"8 9; Check that LSR hoists %t2 computation outside the loop,10; folds %t3's add within the address11; and uses the induction variable (%t4) to access the right element.12define void @test(ptr %ptr.i8, ptr %ptr.float) {13; CHECK-LABEL: define void @test14; CHECK-SAME: (ptr [[PTR_I8:%.*]], ptr [[PTR_FLOAT:%.*]]) {15; CHECK-NEXT: bb:16; CHECK-NEXT: br label [[BB3:%.*]]17; CHECK: bb1:18; CHECK-NEXT: br i1 true, label [[BB10:%.*]], label [[BB2:%.*]]19; CHECK: bb2:20; CHECK-NEXT: [[T:%.*]] = add i64 [[T4:%.*]], 121; CHECK-NEXT: br label [[BB3]]22; CHECK: bb3:23; CHECK-NEXT: [[T4]] = phi i64 [ [[T]], [[BB2]] ], [ 0, [[BB:%.*]] ]24; CHECK-NEXT: br label [[BB1:%.*]]25; CHECK: bb10:26; CHECK-NEXT: [[T7:%.*]] = icmp eq i64 [[T4]], 027; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PTR_I8]], i64 [[T4]]28; CHECK-NEXT: br label [[BB14:%.*]]29; CHECK: bb14:30; CHECK-NEXT: store i8 undef, ptr [[SCEVGEP]], align 131; CHECK-NEXT: [[T6:%.*]] = load ptr, ptr [[PTR_FLOAT]], align 832; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[T6]], i64 1633; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[T4]]34; CHECK-NEXT: store i8 undef, ptr [[SCEVGEP2]], align 135; CHECK-NEXT: br label [[BB14]]36;37bb:38 br label %bb339 40bb1: ; preds = %bb341 br i1 true, label %bb10, label %bb242 43bb2: ; preds = %bb144 %t = add i64 %t4, 1 ; <i64> [#uses=1]45 br label %bb346 47bb3: ; preds = %bb2, %bb48 %t4 = phi i64 [ %t, %bb2 ], [ 0, %bb ] ; <i64> [#uses=3]49 br label %bb150 51bb10: ; preds = %bb952 %t7 = icmp eq i64 %t4, 0 ; <i1> [#uses=1]53 %t3 = add i64 %t4, 16 ; <i64> [#uses=1]54 br label %bb1455 56bb14: ; preds = %bb14, %bb1057 %t2 = getelementptr inbounds i8, ptr %ptr.i8, i64 %t4 ; <ptr> [#uses=1]58 store i8 undef, ptr %t259 %t6 = load ptr, ptr %ptr.float60 %t9 = getelementptr inbounds i8, ptr %t6, i64 %t3 ; <ptr> [#uses=1]61 store i8 undef, ptr %t962 br label %bb1463}64 65; Check that induction variable is initialized to -2.66; IVNEXT covers the uses of %i0 and %t0.67; Therefore, %t0 should be removed and the critical edge must be split.68define fastcc void @TransformLine() nounwind {69; CHECK-LABEL: define fastcc void @TransformLine70; CHECK-SAME: () #[[ATTR0:[0-9]+]] {71; CHECK-NEXT: bb:72; CHECK-NEXT: br label [[LOOP0:%.*]]73; CHECK: loop0:74; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP0]] ], [ -2, [[BB:%.*]] ]75; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 176; CHECK-NEXT: br i1 false, label [[LOOP0]], label [[BB0:%.*]]77; CHECK: bb0:78; CHECK-NEXT: br label [[LOOP1:%.*]]79; CHECK: loop1:80; CHECK-NEXT: [[I1:%.*]] = phi i32 [ 0, [[BB0]] ], [ [[I1_NEXT:%.*]], [[BB5:%.*]] ]81; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[LOOP1_BB6_CRIT_EDGE:%.*]]82; CHECK: bb2:83; CHECK-NEXT: br i1 true, label [[BB6SPLITSPLIT:%.*]], label [[BB5]]84; CHECK: bb5:85; CHECK-NEXT: [[I1_NEXT]] = add i32 [[I1]], 186; CHECK-NEXT: br i1 true, label [[BB5_BB6SPLIT_CRIT_EDGE:%.*]], label [[LOOP1]]87; CHECK: bb5.bb6split_crit_edge:88; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LSR_IV_NEXT]], [[I1_NEXT]]89; CHECK-NEXT: br label [[BB6SPLIT:%.*]]90; CHECK: bb6splitsplit:91; CHECK-NEXT: br label [[BB6SPLIT]]92; CHECK: bb6split:93; CHECK-NEXT: [[P8_PH:%.*]] = phi i32 [ [[TMP0]], [[BB5_BB6SPLIT_CRIT_EDGE]] ], [ undef, [[BB6SPLITSPLIT]] ]94; CHECK-NEXT: [[P9_PH:%.*]] = phi i32 [ undef, [[BB5_BB6SPLIT_CRIT_EDGE]] ], [ [[I1]], [[BB6SPLITSPLIT]] ]95; CHECK-NEXT: br label [[BB6:%.*]]96; CHECK: loop1.bb6_crit_edge:97; CHECK-NEXT: [[I1_LCSSA:%.*]] = phi i32 [ [[I1]], [[LOOP1]] ]98; CHECK-NEXT: br label [[BB6]]99; CHECK: bb6:100; CHECK-NEXT: [[P8:%.*]] = phi i32 [ undef, [[LOOP1_BB6_CRIT_EDGE]] ], [ [[P8_PH]], [[BB6SPLIT]] ]101; CHECK-NEXT: [[P9:%.*]] = phi i32 [ [[I1_LCSSA]], [[LOOP1_BB6_CRIT_EDGE]] ], [ [[P9_PH]], [[BB6SPLIT]] ]102; CHECK-NEXT: unreachable103;104bb:105 br label %loop0106 107loop0: ; preds = %loop0, %bb108 %i0 = phi i32 [ %i0.next, %loop0 ], [ 0, %bb ] ; <i32> [#uses=2]109 %i0.next = add i32 %i0, 1 ; <i32> [#uses=1]110 br i1 false, label %loop0, label %bb0111 112bb0: ; preds = %loop0113 br label %loop1114 115loop1: ; preds = %bb5, %bb0116 %i1 = phi i32 [ 0, %bb0 ], [ %i1.next, %bb5 ] ; <i32> [#uses=4]117 %t0 = add i32 %i0, %i1 ; <i32> [#uses=1]118 br i1 false, label %bb2, label %bb6119 120bb2: ; preds = %loop1121 br i1 true, label %bb6, label %bb5122 123bb5: ; preds = %bb2124 %i1.next = add i32 %i1, 1 ; <i32> [#uses=1]125 br i1 true, label %bb6, label %loop1126 127bb6: ; preds = %bb5, %bb2, %loop1128 %p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0]129 %p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0]130 unreachable131}132